Lines Matching +full:0 +full:x0000003a
10 #define MSR_EFER 0xc0000080 /* extended feature register */
11 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
12 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
13 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
14 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
15 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
16 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
17 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
18 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
21 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
41 #define MSR_TEST_CTRL 0x00000033
45 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
46 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
61 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
62 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
65 #define MSR_PPIN_CTL 0x0000004e
66 #define MSR_PPIN 0x0000004f
68 #define MSR_IA32_PERFCTR0 0x000000c1
69 #define MSR_IA32_PERFCTR1 0x000000c2
70 #define MSR_FSB_FREQ 0x000000cd
71 #define MSR_PLATFORM_INFO 0x000000ce
75 #define MSR_IA32_UMWAIT_CONTROL 0xe1
76 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
80 * bit[1:0] zero.
82 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
85 #define MSR_IA32_CORE_CAPS 0x000000cf
91 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
98 #define MSR_MTRRcap 0x000000fe
100 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
101 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
197 #define MSR_IA32_FLUSH_CMD 0x0000010b
198 #define L1D_FLUSH BIT(0) /*
203 #define MSR_IA32_BBL_CR_CTL 0x00000119
204 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
206 #define MSR_IA32_TSX_CTRL 0x00000122
207 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
210 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
211 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
217 #define MSR_IA32_SYSENTER_CS 0x00000174
218 #define MSR_IA32_SYSENTER_ESP 0x00000175
219 #define MSR_IA32_SYSENTER_EIP 0x00000176
221 #define MSR_IA32_MCG_CAP 0x00000179
222 #define MSR_IA32_MCG_STATUS 0x0000017a
223 #define MSR_IA32_MCG_CTL 0x0000017b
224 #define MSR_ERROR_CONTROL 0x0000017f
225 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
227 #define MSR_OFFCORE_RSP_0 0x000001a6
228 #define MSR_OFFCORE_RSP_1 0x000001a7
229 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
230 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
231 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
233 #define MSR_SNOOP_RSP_0 0x00001328
234 #define MSR_SNOOP_RSP_1 0x00001329
236 #define MSR_LBR_SELECT 0x000001c8
237 #define MSR_LBR_TOS 0x000001c9
239 #define MSR_IA32_POWER_CTL 0x000001fc
243 #define MSR_INTEGRITY_CAPS 0x000002d9
250 #define MSR_LBR_NHM_FROM 0x00000680
251 #define MSR_LBR_NHM_TO 0x000006c0
252 #define MSR_LBR_CORE_FROM 0x00000040
253 #define MSR_LBR_CORE_TO 0x00000060
255 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
260 #define LBR_INFO_CYCLES 0xffff
262 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
264 #define MSR_ARCH_LBR_CTL 0x000014ce
265 #define ARCH_LBR_CTL_LBREN BIT(0)
267 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
269 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
271 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
272 #define MSR_ARCH_LBR_DEPTH 0x000014cf
273 #define MSR_ARCH_LBR_FROM_0 0x00001500
274 #define MSR_ARCH_LBR_TO_0 0x00001600
275 #define MSR_ARCH_LBR_INFO_0 0x00001200
277 #define MSR_IA32_PEBS_ENABLE 0x000003f1
278 #define MSR_PEBS_DATA_CFG 0x000003f2
279 #define MSR_IA32_DS_AREA 0x00000600
280 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
284 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
287 #define PERF_CAP_PEBS_FORMAT 0xf00
292 #define MSR_IA32_RTIT_CTL 0x00000570
293 #define RTIT_CTL_TRACEEN BIT(0)
310 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
312 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
314 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
316 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
318 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
320 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
322 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
323 #define MSR_IA32_RTIT_STATUS 0x00000571
324 #define RTIT_STATUS_FILTEREN BIT(0)
331 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
332 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
333 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
334 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
335 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
336 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
337 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
338 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
339 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
340 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
341 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
342 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
344 #define MSR_MTRRfix64K_00000 0x00000250
345 #define MSR_MTRRfix16K_80000 0x00000258
346 #define MSR_MTRRfix16K_A0000 0x00000259
347 #define MSR_MTRRfix4K_C0000 0x00000268
348 #define MSR_MTRRfix4K_C8000 0x00000269
349 #define MSR_MTRRfix4K_D0000 0x0000026a
350 #define MSR_MTRRfix4K_D8000 0x0000026b
351 #define MSR_MTRRfix4K_E0000 0x0000026c
352 #define MSR_MTRRfix4K_E8000 0x0000026d
353 #define MSR_MTRRfix4K_F0000 0x0000026e
354 #define MSR_MTRRfix4K_F8000 0x0000026f
355 #define MSR_MTRRdefType 0x000002ff
357 #define MSR_IA32_CR_PAT 0x00000277
359 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
360 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
361 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
362 #define MSR_IA32_LASTINTFROMIP 0x000001dd
363 #define MSR_IA32_LASTINTTOIP 0x000001de
365 #define MSR_IA32_PASID 0x00000d93
369 #define DEBUGCTLMSR_LBR_BIT 0 /* last branch recording */
384 #define MSR_PEBS_FRONTEND 0x000003f7
386 #define MSR_IA32_MC0_CTL 0x00000400
387 #define MSR_IA32_MC0_STATUS 0x00000401
388 #define MSR_IA32_MC0_ADDR 0x00000402
389 #define MSR_IA32_MC0_MISC 0x00000403
392 #define MSR_PKG_C3_RESIDENCY 0x000003f8
393 #define MSR_PKG_C6_RESIDENCY 0x000003f9
394 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
395 #define MSR_PKG_C7_RESIDENCY 0x000003fa
396 #define MSR_CORE_C3_RESIDENCY 0x000003fc
397 #define MSR_CORE_C6_RESIDENCY 0x000003fd
398 #define MSR_CORE_C7_RESIDENCY 0x000003fe
399 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
400 #define MSR_PKG_C2_RESIDENCY 0x0000060d
401 #define MSR_PKG_C8_RESIDENCY 0x00000630
402 #define MSR_PKG_C9_RESIDENCY 0x00000631
403 #define MSR_PKG_C10_RESIDENCY 0x00000632
406 #define MSR_PKGC3_IRTL 0x0000060a
407 #define MSR_PKGC6_IRTL 0x0000060b
408 #define MSR_PKGC7_IRTL 0x0000060c
409 #define MSR_PKGC8_IRTL 0x00000633
410 #define MSR_PKGC9_IRTL 0x00000634
411 #define MSR_PKGC10_IRTL 0x00000635
415 #define MSR_VR_CURRENT_CONFIG 0x00000601
416 #define MSR_RAPL_POWER_UNIT 0x00000606
418 #define MSR_PKG_POWER_LIMIT 0x00000610
419 #define MSR_PKG_ENERGY_STATUS 0x00000611
420 #define MSR_PKG_PERF_STATUS 0x00000613
421 #define MSR_PKG_POWER_INFO 0x00000614
423 #define MSR_DRAM_POWER_LIMIT 0x00000618
424 #define MSR_DRAM_ENERGY_STATUS 0x00000619
425 #define MSR_DRAM_PERF_STATUS 0x0000061b
426 #define MSR_DRAM_POWER_INFO 0x0000061c
428 #define MSR_PP0_POWER_LIMIT 0x00000638
429 #define MSR_PP0_ENERGY_STATUS 0x00000639
430 #define MSR_PP0_POLICY 0x0000063a
431 #define MSR_PP0_PERF_STATUS 0x0000063b
433 #define MSR_PP1_POWER_LIMIT 0x00000640
434 #define MSR_PP1_ENERGY_STATUS 0x00000641
435 #define MSR_PP1_POLICY 0x00000642
437 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
438 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
439 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
442 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
443 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
444 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
445 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
446 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
448 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
449 #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
451 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
452 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
453 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
454 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
456 #define MSR_CORE_C1_RES 0x00000660
457 #define MSR_MODULE_C6_RES_MS 0x00000664
459 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
460 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
462 #define MSR_ATOM_CORE_RATIOS 0x0000066a
463 #define MSR_ATOM_CORE_VIDS 0x0000066b
464 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
465 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
467 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
468 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
469 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
472 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
473 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
474 #define CET_SHSTK_EN BIT_ULL(0)
484 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
485 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
486 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
487 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
488 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
491 #define MSR_PPERF 0x0000064e
492 #define MSR_PERF_LIMIT_REASONS 0x0000064f
493 #define MSR_PM_ENABLE 0x00000770
494 #define MSR_HWP_CAPABILITIES 0x00000771
495 #define MSR_HWP_REQUEST_PKG 0x00000772
496 #define MSR_HWP_INTERRUPT 0x00000773
497 #define MSR_HWP_REQUEST 0x00000774
498 #define MSR_HWP_STATUS 0x00000777
508 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
509 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
510 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
511 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
514 #define HWP_MIN_PERF(x) (x & 0xff)
515 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
516 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
517 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
518 #define HWP_EPP_PERFORMANCE 0x00
519 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
520 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
521 #define HWP_EPP_POWERSAVE 0xFF
522 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
523 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
526 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
527 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
530 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
531 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
533 #define MSR_AMD64_MC0_MASK 0xc0010044
543 #define MSR_IA32_MC0_CTL2 0x00000280
546 #define MSR_P6_PERFCTR0 0x000000c1
547 #define MSR_P6_PERFCTR1 0x000000c2
548 #define MSR_P6_EVNTSEL0 0x00000186
549 #define MSR_P6_EVNTSEL1 0x00000187
551 #define MSR_KNC_PERFCTR0 0x00000020
552 #define MSR_KNC_PERFCTR1 0x00000021
553 #define MSR_KNC_EVNTSEL0 0x00000028
554 #define MSR_KNC_EVNTSEL1 0x00000029
557 #define MSR_IA32_PMC0 0x000004c1
560 #define MSR_RELOAD_PMC0 0x000014c1
561 #define MSR_RELOAD_FIXED_CTR0 0x00001309
567 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
568 #define MSR_AMD64_TSC_RATIO 0xc0000104
569 #define MSR_AMD64_NB_CFG 0xc001001f
570 #define MSR_AMD64_PATCH_LOADER 0xc0010020
571 #define MSR_AMD_PERF_CTL 0xc0010062
572 #define MSR_AMD_PERF_STATUS 0xc0010063
573 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
574 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
575 #define MSR_AMD64_OSVW_STATUS 0xc0010141
576 #define MSR_AMD_PPIN_CTL 0xc00102f0
577 #define MSR_AMD_PPIN 0xc00102f1
578 #define MSR_AMD64_CPUID_FN_1 0xc0011004
579 #define MSR_AMD64_LS_CFG 0xc0011020
580 #define MSR_AMD64_DC_CFG 0xc0011022
581 #define MSR_AMD64_TW_CFG 0xc0011023
583 #define MSR_AMD64_DE_CFG 0xc0011029
588 #define MSR_AMD64_BU_CFG2 0xc001102a
589 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
590 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
591 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
594 #define MSR_AMD64_IBSOPCTL 0xc0011033
595 #define MSR_AMD64_IBSOPRIP 0xc0011034
596 #define MSR_AMD64_IBSOPDATA 0xc0011035
597 #define MSR_AMD64_IBSOPDATA2 0xc0011036
598 #define MSR_AMD64_IBSOPDATA3 0xc0011037
599 #define MSR_AMD64_IBSDCLINAD 0xc0011038
600 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
603 #define MSR_AMD64_IBSCTL 0xc001103a
604 #define MSR_AMD64_IBSBRTARGET 0xc001103b
605 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
606 #define MSR_AMD64_IBSOPDATA4 0xc001103d
608 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
609 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
610 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130
611 #define MSR_AMD64_SEV 0xc0010131
612 #define MSR_AMD64_SEV_ENABLED_BIT 0
639 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
642 #define MSR_AMD_CPPC_CAP1 0xc00102b0
643 #define MSR_AMD_CPPC_ENABLE 0xc00102b1
644 #define MSR_AMD_CPPC_CAP2 0xc00102b2
645 #define MSR_AMD_CPPC_REQ 0xc00102b3
646 #define MSR_AMD_CPPC_STATUS 0xc00102b4
648 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
649 #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
650 #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
651 #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
653 #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
654 #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
655 #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
656 #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
659 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
660 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
661 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
664 #define MSR_AMD64_LBR_SELECT 0xc000010e
667 #define MSR_ZEN4_BP_CFG 0xc001102e
671 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
675 #define MSR_F17H_IRPERF 0xc00000e9
678 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
679 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
680 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
681 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
682 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
683 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
686 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
687 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
688 #define MSR_F15H_PERF_CTL 0xc0010200
696 #define MSR_F15H_PERF_CTR 0xc0010201
704 #define MSR_F15H_NB_PERF_CTL 0xc0010240
705 #define MSR_F15H_NB_PERF_CTR 0xc0010241
706 #define MSR_F15H_PTSC 0xc0010280
707 #define MSR_F15H_IC_CFG 0xc0011021
708 #define MSR_F15H_EX_CFG 0xc001102c
711 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
712 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
713 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
715 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
717 #define MSR_FAM10H_NODE_ID 0xc001100c
720 #define MSR_K8_TOP_MEM1 0xc001001a
721 #define MSR_K8_TOP_MEM2 0xc001001d
722 #define MSR_AMD64_SYSCFG 0xc0010010
725 #define MSR_K8_INT_PENDING_MSG 0xc0010055
727 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
728 #define MSR_K8_TSEG_ADDR 0xc0010112
729 #define MSR_K8_TSEG_MASK 0xc0010113
730 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
731 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
732 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
735 #define MSR_K7_EVNTSEL0 0xc0010000
736 #define MSR_K7_PERFCTR0 0xc0010004
737 #define MSR_K7_EVNTSEL1 0xc0010001
738 #define MSR_K7_PERFCTR1 0xc0010005
739 #define MSR_K7_EVNTSEL2 0xc0010002
740 #define MSR_K7_PERFCTR2 0xc0010006
741 #define MSR_K7_EVNTSEL3 0xc0010003
742 #define MSR_K7_PERFCTR3 0xc0010007
743 #define MSR_K7_CLK_CTL 0xc001001b
744 #define MSR_K7_HWCR 0xc0010015
745 #define MSR_K7_HWCR_SMMLOCK_BIT 0
749 #define MSR_K7_FID_VID_CTL 0xc0010041
750 #define MSR_K7_FID_VID_STATUS 0xc0010042
753 #define MSR_K6_WHCR 0xc0000082
754 #define MSR_K6_UWCCR 0xc0000085
755 #define MSR_K6_EPMR 0xc0000086
756 #define MSR_K6_PSOR 0xc0000087
757 #define MSR_K6_PFIR 0xc0000088
760 #define MSR_IDT_FCR1 0x00000107
761 #define MSR_IDT_FCR2 0x00000108
762 #define MSR_IDT_FCR3 0x00000109
763 #define MSR_IDT_FCR4 0x0000010a
765 #define MSR_IDT_MCR0 0x00000110
766 #define MSR_IDT_MCR1 0x00000111
767 #define MSR_IDT_MCR2 0x00000112
768 #define MSR_IDT_MCR3 0x00000113
769 #define MSR_IDT_MCR4 0x00000114
770 #define MSR_IDT_MCR5 0x00000115
771 #define MSR_IDT_MCR6 0x00000116
772 #define MSR_IDT_MCR7 0x00000117
773 #define MSR_IDT_MCR_CTRL 0x00000120
776 #define MSR_VIA_FCR 0x00001107
777 #define MSR_VIA_LONGHAUL 0x0000110a
778 #define MSR_VIA_RNG 0x0000110b
779 #define MSR_VIA_BCR2 0x00001147
782 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
783 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
784 #define MSR_TMTA_LRTI_READOUT 0x80868018
785 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
788 #define MSR_IA32_P5_MC_ADDR 0x00000000
789 #define MSR_IA32_P5_MC_TYPE 0x00000001
790 #define MSR_IA32_TSC 0x00000010
791 #define MSR_IA32_PLATFORM_ID 0x00000017
792 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
793 #define MSR_EBC_FREQUENCY_ID 0x0000002c
794 #define MSR_SMI_COUNT 0x00000034
797 #define MSR_IA32_FEAT_CTL 0x0000003a
798 #define FEAT_CTL_LOCKED BIT(0)
805 #define MSR_IA32_TSC_ADJUST 0x0000003b
806 #define MSR_IA32_BNDCFGS 0x00000d90
808 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
810 #define MSR_IA32_XFD 0x000001c4
811 #define MSR_IA32_XFD_ERR 0x000001c5
812 #define MSR_IA32_XSS 0x00000da0
814 #define MSR_IA32_APICBASE 0x0000001b
817 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
819 #define MSR_IA32_UCODE_WRITE 0x00000079
820 #define MSR_IA32_UCODE_REV 0x0000008b
823 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
824 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
825 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
826 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
828 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
829 #define MSR_IA32_SMBASE 0x0000009e
831 #define MSR_IA32_PERF_STATUS 0x00000198
832 #define MSR_IA32_PERF_CTL 0x00000199
833 #define INTEL_PERF_CTL_MASK 0xffff
836 #define MSR_AMD_DBG_EXTN_CFG 0xc000010f
837 #define MSR_AMD_SAMP_BR_FROM 0xc0010300
841 #define MSR_IA32_MPERF 0x000000e7
842 #define MSR_IA32_APERF 0x000000e8
844 #define MSR_IA32_THERM_CONTROL 0x0000019a
845 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
847 #define THERM_INT_HIGH_ENABLE (1 << 0)
851 #define MSR_IA32_THERM_STATUS 0x0000019c
853 #define THERM_STATUS_PROCHOT (1 << 0)
856 #define MSR_THERM2_CTL 0x0000019d
860 #define MSR_IA32_MISC_ENABLE 0x000001a0
862 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
864 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
865 #define MSR_MISC_PWR_MGMT 0x000001aa
867 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
868 #define ENERGY_PERF_BIAS_PERFORMANCE 0
875 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
877 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
881 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
883 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
891 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
894 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
901 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
955 #define MSR_MISC_FEATURES_ENABLES 0x00000140
957 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
961 #define MSR_IA32_TSC_DEADLINE 0x000006E0
964 #define MSR_TSX_FORCE_ABORT 0x0000010F
966 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
974 #define MSR_IA32_MCG_EAX 0x00000180
975 #define MSR_IA32_MCG_EBX 0x00000181
976 #define MSR_IA32_MCG_ECX 0x00000182
977 #define MSR_IA32_MCG_EDX 0x00000183
978 #define MSR_IA32_MCG_ESI 0x00000184
979 #define MSR_IA32_MCG_EDI 0x00000185
980 #define MSR_IA32_MCG_EBP 0x00000186
981 #define MSR_IA32_MCG_ESP 0x00000187
982 #define MSR_IA32_MCG_EFLAGS 0x00000188
983 #define MSR_IA32_MCG_EIP 0x00000189
984 #define MSR_IA32_MCG_RESERVED 0x0000018a
987 #define MSR_P4_BPU_PERFCTR0 0x00000300
988 #define MSR_P4_BPU_PERFCTR1 0x00000301
989 #define MSR_P4_BPU_PERFCTR2 0x00000302
990 #define MSR_P4_BPU_PERFCTR3 0x00000303
991 #define MSR_P4_MS_PERFCTR0 0x00000304
992 #define MSR_P4_MS_PERFCTR1 0x00000305
993 #define MSR_P4_MS_PERFCTR2 0x00000306
994 #define MSR_P4_MS_PERFCTR3 0x00000307
995 #define MSR_P4_FLAME_PERFCTR0 0x00000308
996 #define MSR_P4_FLAME_PERFCTR1 0x00000309
997 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
998 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
999 #define MSR_P4_IQ_PERFCTR0 0x0000030c
1000 #define MSR_P4_IQ_PERFCTR1 0x0000030d
1001 #define MSR_P4_IQ_PERFCTR2 0x0000030e
1002 #define MSR_P4_IQ_PERFCTR3 0x0000030f
1003 #define MSR_P4_IQ_PERFCTR4 0x00000310
1004 #define MSR_P4_IQ_PERFCTR5 0x00000311
1005 #define MSR_P4_BPU_CCCR0 0x00000360
1006 #define MSR_P4_BPU_CCCR1 0x00000361
1007 #define MSR_P4_BPU_CCCR2 0x00000362
1008 #define MSR_P4_BPU_CCCR3 0x00000363
1009 #define MSR_P4_MS_CCCR0 0x00000364
1010 #define MSR_P4_MS_CCCR1 0x00000365
1011 #define MSR_P4_MS_CCCR2 0x00000366
1012 #define MSR_P4_MS_CCCR3 0x00000367
1013 #define MSR_P4_FLAME_CCCR0 0x00000368
1014 #define MSR_P4_FLAME_CCCR1 0x00000369
1015 #define MSR_P4_FLAME_CCCR2 0x0000036a
1016 #define MSR_P4_FLAME_CCCR3 0x0000036b
1017 #define MSR_P4_IQ_CCCR0 0x0000036c
1018 #define MSR_P4_IQ_CCCR1 0x0000036d
1019 #define MSR_P4_IQ_CCCR2 0x0000036e
1020 #define MSR_P4_IQ_CCCR3 0x0000036f
1021 #define MSR_P4_IQ_CCCR4 0x00000370
1022 #define MSR_P4_IQ_CCCR5 0x00000371
1023 #define MSR_P4_ALF_ESCR0 0x000003ca
1024 #define MSR_P4_ALF_ESCR1 0x000003cb
1025 #define MSR_P4_BPU_ESCR0 0x000003b2
1026 #define MSR_P4_BPU_ESCR1 0x000003b3
1027 #define MSR_P4_BSU_ESCR0 0x000003a0
1028 #define MSR_P4_BSU_ESCR1 0x000003a1
1029 #define MSR_P4_CRU_ESCR0 0x000003b8
1030 #define MSR_P4_CRU_ESCR1 0x000003b9
1031 #define MSR_P4_CRU_ESCR2 0x000003cc
1032 #define MSR_P4_CRU_ESCR3 0x000003cd
1033 #define MSR_P4_CRU_ESCR4 0x000003e0
1034 #define MSR_P4_CRU_ESCR5 0x000003e1
1035 #define MSR_P4_DAC_ESCR0 0x000003a8
1036 #define MSR_P4_DAC_ESCR1 0x000003a9
1037 #define MSR_P4_FIRM_ESCR0 0x000003a4
1038 #define MSR_P4_FIRM_ESCR1 0x000003a5
1039 #define MSR_P4_FLAME_ESCR0 0x000003a6
1040 #define MSR_P4_FLAME_ESCR1 0x000003a7
1041 #define MSR_P4_FSB_ESCR0 0x000003a2
1042 #define MSR_P4_FSB_ESCR1 0x000003a3
1043 #define MSR_P4_IQ_ESCR0 0x000003ba
1044 #define MSR_P4_IQ_ESCR1 0x000003bb
1045 #define MSR_P4_IS_ESCR0 0x000003b4
1046 #define MSR_P4_IS_ESCR1 0x000003b5
1047 #define MSR_P4_ITLB_ESCR0 0x000003b6
1048 #define MSR_P4_ITLB_ESCR1 0x000003b7
1049 #define MSR_P4_IX_ESCR0 0x000003c8
1050 #define MSR_P4_IX_ESCR1 0x000003c9
1051 #define MSR_P4_MOB_ESCR0 0x000003aa
1052 #define MSR_P4_MOB_ESCR1 0x000003ab
1053 #define MSR_P4_MS_ESCR0 0x000003c0
1054 #define MSR_P4_MS_ESCR1 0x000003c1
1055 #define MSR_P4_PMH_ESCR0 0x000003ac
1056 #define MSR_P4_PMH_ESCR1 0x000003ad
1057 #define MSR_P4_RAT_ESCR0 0x000003bc
1058 #define MSR_P4_RAT_ESCR1 0x000003bd
1059 #define MSR_P4_SAAT_ESCR0 0x000003ae
1060 #define MSR_P4_SAAT_ESCR1 0x000003af
1061 #define MSR_P4_SSU_ESCR0 0x000003be
1062 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
1064 #define MSR_P4_TBPU_ESCR0 0x000003c2
1065 #define MSR_P4_TBPU_ESCR1 0x000003c3
1066 #define MSR_P4_TC_ESCR0 0x000003c4
1067 #define MSR_P4_TC_ESCR1 0x000003c5
1068 #define MSR_P4_U2L_ESCR0 0x000003b0
1069 #define MSR_P4_U2L_ESCR1 0x000003b1
1071 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
1074 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
1075 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
1076 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
1077 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
1078 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
1079 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
1080 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
1081 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
1083 #define MSR_PERF_METRICS 0x00000329
1094 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
1097 #define MSR_IA32_VMX_BASIC 0x00000480
1098 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
1099 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
1100 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
1101 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
1102 #define MSR_IA32_VMX_MISC 0x00000485
1103 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
1104 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
1105 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
1106 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
1107 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
1108 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
1109 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
1110 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
1111 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
1112 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
1113 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
1114 #define MSR_IA32_VMX_VMFUNC 0x00000491
1115 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
1120 #define VMX_BASIC_64 0x0001000000000000LLU
1122 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
1124 #define VMX_BASIC_INOUT 0x0040000000000000LLU
1128 #define MSR_IA32_L3_QOS_CFG 0xc81
1129 #define MSR_IA32_L2_QOS_CFG 0xc82
1130 #define MSR_IA32_QM_EVTSEL 0xc8d
1131 #define MSR_IA32_QM_CTR 0xc8e
1132 #define MSR_IA32_PQR_ASSOC 0xc8f
1133 #define MSR_IA32_L3_CBM_BASE 0xc90
1134 #define MSR_IA32_L2_CBM_BASE 0xd10
1135 #define MSR_IA32_MBA_THRTL_BASE 0xd50
1138 #define MSR_IA32_MBA_BW_BASE 0xc0000200
1139 #define MSR_IA32_SMBA_BW_BASE 0xc0000280
1140 #define MSR_IA32_EVT_CFG_BASE 0xc0000400
1145 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
1148 #define MSR_VM_CR 0xc0010114
1149 #define MSR_VM_IGNNE 0xc0010115
1150 #define MSR_VM_HSAVE_PA 0xc0010117
1153 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
1154 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
1157 #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
1158 #define LEGACY_XAPIC_DISABLED BIT(0) /*