Lines Matching refs:P

72 #define P(a, b) PERF_MEM_S(a, b)  macro
73 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
74 #define LEVEL(x) P(LVLNUM, x)
75 #define REM P(REMOTE, REMOTE)
76 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
80 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
81 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
82 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
83 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
84 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
85 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
86 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
87 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
88 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
89 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
90 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
91 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
92 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
93 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
94 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
95 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
101 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
102 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
103 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
110 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_skl()
111 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_skl()
112 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); in __intel_pmu_pebs_data_source_skl()
113 data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_skl()
114 data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_skl()
124 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_grt()
125 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_grt()
126 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_grt()
149 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_cmt()
150 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_cmt()
151 data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE); in __intel_pmu_pebs_data_source_cmt()
152 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); in __intel_pmu_pebs_data_source_cmt()
153 data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_cmt()
154 data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_cmt()
178 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); in precise_store_data()
190 val |= P(TLB, MISS); in precise_store_data()
192 val |= P(TLB, HIT); in precise_store_data()
200 val |= P(LVL, HIT); in precise_store_data()
202 val |= P(LVL, MISS); in precise_store_data()
208 val |= P(LOCK, LOCKED); in precise_store_data()
249 *val |= P(TLB, MISS) | P(TLB, L2); in pebs_set_tlb_lock()
251 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in pebs_set_tlb_lock()
255 *val |= P(LOCK, LOCKED); in pebs_set_tlb_lock()
272 val |= P(BLK, DATA); in __adl_latency_data_small()
274 val |= P(BLK, NA); in __adl_latency_data_small()
318 val |= P(TLB, NA) | P(LOCK, NA); in load_latency_data()
328 val |= P(BLK, NA); in load_latency_data()
336 val |= P(BLK, DATA); in load_latency_data()
343 val |= P(BLK, ADDR); in load_latency_data()
346 val |= P(BLK, NA); in load_latency_data()
366 val |= P(BLK, NA); in store_latency_data()
373 src.mem_op = P(OP,STORE); in store_latency_data()