Lines Matching refs:PA_FPGA
47 #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ macro
50 #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
51 #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
52 #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
53 #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
54 #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
55 #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
56 #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
57 #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
58 #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
59 #define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
60 #define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
61 #define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
62 #define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
64 #define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
65 #define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
66 #define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */