Lines Matching +full:disable +full:- +full:timing +full:- +full:generator

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5  * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
81 /* DISPLAY-ENABLE polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
148 	 * Display Enable signal (default high-active)  DISPEN_LOWACT
149 	 * Display Data signals (default high-active)   DPOL_LOWACT
151 	 * Hsync-During-Vsync suppression (default off) CL1CNT
152 	 * Vsync-during-vsync suppression (default off) CL2CNT
163 	/* LDPMMR and LDPSPR control the timing of the power signals
192 	 * more than the LCDC in terms of blanking (e.g. disable clock
193 	 * generator / backlight power supply / etc.