149 	struct pnv_iov_data *iov;  in pnv_pci_ioda_fixup_iov_resources()  local
152 	iov = kzalloc(sizeof(*iov), GFP_KERNEL);  in pnv_pci_ioda_fixup_iov_resources()
153 	if (!iov)  in pnv_pci_ioda_fixup_iov_resources()
155 	pdev->dev.archdata.iov_data = iov;  in pnv_pci_ioda_fixup_iov_resources()
194 			iov->m64_single_mode[i] = true;  in pnv_pci_ioda_fixup_iov_resources()
209 		iov->need_shift = true;  in pnv_pci_ioda_fixup_iov_resources()
223 	kfree(iov);  in pnv_pci_ioda_fixup_iov_resources()
252 	struct pnv_iov_data *iov = pnv_iov_get(pdev);  in pnv_pci_iov_resource_alignment()  local
260 	if (!iov)  in pnv_pci_iov_resource_alignment()
268 	if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES])  in pnv_pci_iov_resource_alignment()
286 	struct pnv_iov_data   *iov;  in pnv_pci_vf_release_m64()  local
291 	iov = pnv_iov_get(pdev);  in pnv_pci_vf_release_m64()
293 	for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {  in pnv_pci_vf_release_m64()
398 static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)  in pnv_pci_alloc_m64_bar()  argument
410 	set_bit(win, iov->used_m64_bar_mask);  in pnv_pci_alloc_m64_bar()
417 	struct pnv_iov_data   *iov;  in pnv_pci_vf_assign_m64()  local
427 	iov = pnv_iov_get(pdev);  in pnv_pci_vf_assign_m64()
435 		if (!iov->m64_single_mode[i]) {  in pnv_pci_vf_assign_m64()
436 			win = pnv_pci_alloc_m64_bar(phb, iov);  in pnv_pci_vf_assign_m64()
452 		base_pe_num = iov->vf_pe_arr[0].pe_number;  in pnv_pci_vf_assign_m64()
455 			win = pnv_pci_alloc_m64_bar(phb, iov);  in pnv_pci_vf_assign_m64()
506 	struct pnv_iov_data *iov;  in pnv_pci_vf_resource_shift()  local
513 	iov = pnv_iov_get(dev);  in pnv_pci_vf_resource_shift()
523 	num_vfs = iov->num_vfs;  in pnv_pci_vf_resource_shift()
528 		if (iov->m64_single_mode[i])  in pnv_pci_vf_resource_shift()
561 		if (iov->m64_single_mode[i])  in pnv_pci_vf_resource_shift()
573 			devm_release_resource(&dev->dev, &iov->holes[i]);  in pnv_pci_vf_resource_shift()
574 			memset(&iov->holes[i], 0, sizeof(iov->holes[i]));  in pnv_pci_vf_resource_shift()
580 			iov->holes[i].start = res2.start;  in pnv_pci_vf_resource_shift()
581 			iov->holes[i].end = res2.start + size * offset - 1;  in pnv_pci_vf_resource_shift()
582 			iov->holes[i].flags = IORESOURCE_BUS;  in pnv_pci_vf_resource_shift()
583 			iov->holes[i].name = "pnv_iov_reserved";  in pnv_pci_vf_resource_shift()
585 					&iov->holes[i]);  in pnv_pci_vf_resource_shift()
594 	struct pnv_iov_data   *iov;  in pnv_pci_sriov_disable()  local
596 	iov = pnv_iov_get(pdev);  in pnv_pci_sriov_disable()
597 	if (WARN_ON(!iov))  in pnv_pci_sriov_disable()
600 	num_vfs = iov->num_vfs;  in pnv_pci_sriov_disable()
601 	base_pe = iov->vf_pe_arr[0].pe_number;  in pnv_pci_sriov_disable()
607 	if (iov->need_shift)  in pnv_pci_sriov_disable()
620 	struct pnv_iov_data   *iov;  in pnv_ioda_setup_vf_PE()  local
628 	iov = pnv_iov_get(pdev);  in pnv_ioda_setup_vf_PE()
636 		pe = &iov->vf_pe_arr[vf_index];  in pnv_ioda_setup_vf_PE()
677 	struct pnv_iov_data   *iov;  in pnv_pci_sriov_enable()  local
683 	iov = pnv_iov_get(pdev);  in pnv_pci_sriov_enable()
697 	if (!iov) {  in pnv_pci_sriov_enable()
709 	iov->vf_pe_arr = base_pe;  in pnv_pci_sriov_enable()
710 	iov->num_vfs = num_vfs;  in pnv_pci_sriov_enable()
724 	if (iov->need_shift) {  in pnv_pci_sriov_enable()
740 		pnv_ioda_free_pe(&iov->vf_pe_arr[i]);  in pnv_pci_sriov_enable()