Lines Matching +full:compound +full:- +full:device
1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #include <asm/ppc-pci.h>
34 #include <asm/pnv-pci.h>
40 static int eeh_event_irq = -EINVAL;
44 dev_dbg(&pdev->dev, "EEH: Setting up device\n"); in pnv_pcibios_bus_add_device()
69 struct pci_controller *hose = filp->private_data; in pnv_eeh_ei_write()
76 if (!eeh_ops || !eeh_ops->err_inject) in pnv_eeh_ei_write()
77 return -ENXIO; in pnv_eeh_ei_write()
82 return -EFAULT; in pnv_eeh_ei_write()
88 return -EINVAL; in pnv_eeh_ei_write()
93 return -ENODEV; in pnv_eeh_ei_write()
96 ret = eeh_ops->err_inject(pe, type, func, addr, mask); in pnv_eeh_ei_write()
109 struct pnv_phb *phb = hose->private_data; in pnv_eeh_dbgfs_set()
111 out_be64(phb->regs + offset, val); in pnv_eeh_dbgfs_set()
118 struct pnv_phb *phb = hose->private_data; in pnv_eeh_dbgfs_get()
120 *val = in_be64(phb->regs + offset); in pnv_eeh_dbgfs_get()
152 phb = hose->private_data; in pnv_eeh_enable_phbs()
159 phb->flags |= PNV_PHB_FLAG_EEH; in pnv_eeh_enable_phbs()
161 phb->flags &= ~PNV_PHB_FLAG_EEH; in pnv_eeh_enable_phbs()
166 * pnv_eeh_post_init - EEH platform dependent post initialization
190 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); in pnv_eeh_post_init()
204 phb = hose->private_data; in pnv_eeh_post_init()
208 if (phb->has_dbgfs || !phb->dbgfs) in pnv_eeh_post_init()
211 phb->has_dbgfs = 1; in pnv_eeh_post_init()
213 phb->dbgfs, hose, in pnv_eeh_post_init()
217 phb->dbgfs, hose, in pnv_eeh_post_init()
220 phb->dbgfs, hose, in pnv_eeh_post_init()
223 phb->dbgfs, hose, in pnv_eeh_post_init()
240 /* Check if the device supports capabilities */ in pnv_eeh_find_cap()
245 while (cnt--) { in pnv_eeh_find_cap()
270 int pos = 256, ttl = (4096 - 256) / 8; in pnv_eeh_find_ecap()
272 if (!edev || !edev->pcie_cap) in pnv_eeh_find_ecap()
279 while (ttl-- > 0) { in pnv_eeh_find_ecap()
296 struct pci_controller *hose = pdev->bus->sysdata; in pnv_eeh_get_upstream_pe()
297 struct pnv_phb *phb = hose->private_data; in pnv_eeh_get_upstream_pe()
298 struct pci_dev *parent = pdev->bus->self; in pnv_eeh_get_upstream_pe()
302 if (pdev->is_virtfn) in pnv_eeh_get_upstream_pe()
303 parent = pdev->physfn; in pnv_eeh_get_upstream_pe()
310 return eeh_pe_get(phb->hose, ioda_pe->pe_number); in pnv_eeh_get_upstream_pe()
317 * pnv_eeh_probe - Do probe on PCI device
325 struct pci_controller *hose = pdn->phb; in pnv_eeh_probe()
326 struct pnv_phb *phb = hose->private_data; in pnv_eeh_probe()
331 int config_addr = (pdn->busno << 8) | (pdn->devfn); in pnv_eeh_probe()
339 if (!edev || edev->pe) in pnv_eeh_probe()
343 if (edev->pdev) { in pnv_eeh_probe()
345 __func__, hose->global_number, config_addr >> 8, in pnv_eeh_probe()
350 /* Skip for PCI-ISA bridge */ in pnv_eeh_probe()
351 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) in pnv_eeh_probe()
354 eeh_edev_dbg(edev, "Probing device\n"); in pnv_eeh_probe()
356 /* Initialize eeh device */ in pnv_eeh_probe()
357 edev->mode &= 0xFFFFFF00; in pnv_eeh_probe()
358 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); in pnv_eeh_probe()
359 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); in pnv_eeh_probe()
360 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); in pnv_eeh_probe()
361 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); in pnv_eeh_probe()
362 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in pnv_eeh_probe()
363 edev->mode |= EEH_DEV_BRIDGE; in pnv_eeh_probe()
364 if (edev->pcie_cap) { in pnv_eeh_probe()
365 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, in pnv_eeh_probe()
369 edev->mode |= EEH_DEV_ROOT_PORT; in pnv_eeh_probe()
371 edev->mode |= EEH_DEV_DS_PORT; in pnv_eeh_probe()
375 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; in pnv_eeh_probe()
382 eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); in pnv_eeh_probe()
399 * Broadcom BCM5718 2-ports NICs (14e4:1656) in pnv_eeh_probe()
400 * Broadcom Austin 4-ports NICs (14e4:1657) in pnv_eeh_probe()
401 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) in pnv_eeh_probe()
402 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) in pnv_eeh_probe()
404 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
405 pdn->device_id == 0x1656) || in pnv_eeh_probe()
406 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
407 pdn->device_id == 0x1657) || in pnv_eeh_probe()
408 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
409 pdn->device_id == 0x168a) || in pnv_eeh_probe()
410 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && in pnv_eeh_probe()
411 pdn->device_id == 0x168e)) in pnv_eeh_probe()
412 edev->pe->state |= EEH_PE_CFG_RESTRICTED; in pnv_eeh_probe()
420 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { in pnv_eeh_probe()
421 edev->pe->bus = pci_find_bus(hose->global_number, in pnv_eeh_probe()
422 pdn->busno); in pnv_eeh_probe()
423 if (edev->pe->bus) in pnv_eeh_probe()
424 edev->pe->state |= EEH_PE_PRI_BUS; in pnv_eeh_probe()
440 eeh_edev_dbg(edev, "EEH enabled on device\n"); in pnv_eeh_probe()
446 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
456 struct pci_controller *hose = pe->phb; in pnv_eeh_set_option()
457 struct pnv_phb *phb = hose->private_data; in pnv_eeh_set_option()
464 return -EPERM; in pnv_eeh_set_option()
479 return -EINVAL; in pnv_eeh_set_option()
482 /* Freeze master and slave PEs if PHB supports compound PEs */ in pnv_eeh_set_option()
484 if (phb->freeze_pe) { in pnv_eeh_set_option()
485 phb->freeze_pe(phb, pe->addr); in pnv_eeh_set_option()
489 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); in pnv_eeh_set_option()
491 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_eeh_set_option()
492 __func__, rc, phb->hose->global_number, in pnv_eeh_set_option()
493 pe->addr); in pnv_eeh_set_option()
494 return -EIO; in pnv_eeh_set_option()
501 if (phb->unfreeze_pe) in pnv_eeh_set_option()
502 return phb->unfreeze_pe(phb, pe->addr, opt); in pnv_eeh_set_option()
504 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); in pnv_eeh_set_option()
506 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", in pnv_eeh_set_option()
507 __func__, rc, option, phb->hose->global_number, in pnv_eeh_set_option()
508 pe->addr); in pnv_eeh_set_option()
509 return -EIO; in pnv_eeh_set_option()
517 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_phb_diag()
520 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, in pnv_eeh_get_phb_diag()
521 phb->diag_data_size); in pnv_eeh_get_phb_diag()
523 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", in pnv_eeh_get_phb_diag()
524 __func__, rc, pe->phb->global_number); in pnv_eeh_get_phb_diag()
529 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_phb_state()
535 rc = opal_pci_eeh_freeze_status(phb->opal_id, in pnv_eeh_get_phb_state()
536 pe->addr, in pnv_eeh_get_phb_state()
542 __func__, rc, phb->hose->global_number); in pnv_eeh_get_phb_state()
548 * first time, to dump the PHB diag-data. in pnv_eeh_get_phb_state()
555 } else if (!(pe->state & EEH_PE_ISOLATED)) { in pnv_eeh_get_phb_state()
560 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_phb_state()
568 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_pe_state()
580 if (pe->state & EEH_PE_RESET) { in pnv_eeh_get_pe_state()
590 * supports compound PE, let it handle that. in pnv_eeh_get_pe_state()
592 if (phb->get_pe_state) { in pnv_eeh_get_pe_state()
593 fstate = phb->get_pe_state(phb, pe->addr); in pnv_eeh_get_pe_state()
595 rc = opal_pci_eeh_freeze_status(phb->opal_id, in pnv_eeh_get_pe_state()
596 pe->addr, in pnv_eeh_get_pe_state()
601 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", in pnv_eeh_get_pe_state()
602 __func__, rc, phb->hose->global_number, in pnv_eeh_get_pe_state()
603 pe->addr); in pnv_eeh_get_pe_state()
638 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", in pnv_eeh_get_pe_state()
639 __func__, phb->hose->global_number, in pnv_eeh_get_pe_state()
640 pe->addr, fstate); in pnv_eeh_get_pe_state()
644 * If PHB supports compound PE, to freeze all in pnv_eeh_get_pe_state()
648 * first time, to dump the PHB diag-data. in pnv_eeh_get_pe_state()
654 !(pe->state & EEH_PE_ISOLATED)) { in pnv_eeh_get_pe_state()
655 if (phb->freeze_pe) in pnv_eeh_get_pe_state()
656 phb->freeze_pe(phb, pe->addr); in pnv_eeh_get_pe_state()
662 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_pe_state()
669 * pnv_eeh_get_state - Retrieve PE state
673 * Retrieve the state of the specified PE. For IODA-compitable
682 if (pe->type & EEH_PE_PHB) in pnv_eeh_get_state()
722 struct pnv_phb *phb = hose->private_data; in pnv_eeh_phb_reset()
726 __func__, hose->global_number, option); in pnv_eeh_phb_reset()
731 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_phb_reset()
735 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_phb_reset()
748 rc = pnv_eeh_poll(phb->opal_id); in pnv_eeh_phb_reset()
757 return -EIO; in pnv_eeh_phb_reset()
764 struct pnv_phb *phb = hose->private_data; in pnv_eeh_root_reset()
768 __func__, hose->global_number, option); in pnv_eeh_root_reset()
776 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_root_reset()
780 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_root_reset()
784 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_root_reset()
792 rc = pnv_eeh_poll(phb->opal_id); in pnv_eeh_root_reset()
797 return -EIO; in pnv_eeh_root_reset()
804 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); in __pnv_eeh_bridge_reset()
806 int aer = edev ? edev->aer_cap : 0; in __pnv_eeh_bridge_reset()
810 __func__, pci_domain_nr(dev->bus), in __pnv_eeh_bridge_reset()
811 dev->bus->number, option); in __pnv_eeh_bridge_reset()
818 eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
821 eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
825 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); in __pnv_eeh_bridge_reset()
827 eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); in __pnv_eeh_bridge_reset()
832 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); in __pnv_eeh_bridge_reset()
834 eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); in __pnv_eeh_bridge_reset()
840 eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
843 eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, in __pnv_eeh_bridge_reset()
855 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pnv_eeh_bridge_reset()
856 struct pnv_phb *phb = hose->private_data; in pnv_eeh_bridge_reset()
858 uint64_t id = PCI_SLOT_ID(phb->opal_id, pci_dev_id(pdev)); in pnv_eeh_bridge_reset()
863 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) in pnv_eeh_bridge_reset()
867 __func__, pci_domain_nr(pdev->bus), in pnv_eeh_bridge_reset()
868 pdev->bus->number, option); in pnv_eeh_bridge_reset()
880 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", in pnv_eeh_bridge_reset()
882 return -EINVAL; in pnv_eeh_bridge_reset()
891 return (rc == OPAL_SUCCESS) ? 0 : -EIO; in pnv_eeh_bridge_reset()
898 if (pci_is_root_bus(dev->bus)) { in pnv_pci_reset_secondary_bus()
899 hose = pci_bus_to_host(dev->bus); in pnv_pci_reset_secondary_bus()
911 struct eeh_dev *edev = pdn->edev; in pnv_eeh_wait_for_pending()
916 eeh_ops->read_config(edev, pos, 2, &status); in pnv_eeh_wait_for_pending()
925 pdn->phb->global_number, pdn->busno, in pnv_eeh_wait_for_pending()
926 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); in pnv_eeh_wait_for_pending()
934 if (WARN_ON(!edev->pcie_cap)) in pnv_eeh_do_flr()
935 return -ENOTTY; in pnv_eeh_do_flr()
937 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); in pnv_eeh_do_flr()
939 return -ENOTTY; in pnv_eeh_do_flr()
945 edev->pcie_cap + PCI_EXP_DEVSTA, in pnv_eeh_do_flr()
947 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
950 eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
955 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
958 eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, in pnv_eeh_do_flr()
972 if (WARN_ON(!edev->af_cap)) in pnv_eeh_do_af_flr()
973 return -ENOTTY; in pnv_eeh_do_af_flr()
975 eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap); in pnv_eeh_do_af_flr()
977 return -ENOTTY; in pnv_eeh_do_af_flr()
983 * Wait for Transaction Pending bit to clear. A word-aligned in pnv_eeh_do_af_flr()
988 edev->af_cap + PCI_AF_CTRL, in pnv_eeh_do_af_flr()
990 eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, in pnv_eeh_do_af_flr()
995 eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0); in pnv_eeh_do_af_flr()
1009 /* The VF PE should have only one child device */ in pnv_eeh_reset_vf_pe()
1010 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); in pnv_eeh_reset_vf_pe()
1013 return -ENXIO; in pnv_eeh_reset_vf_pe()
1023 * pnv_eeh_reset - Reset the specified PE
1030 * PCI device sensitive PE, we will try to reset the device
1036 struct pci_controller *hose = pe->phb; in pnv_eeh_reset()
1055 if (pe->type & EEH_PE_PHB) in pnv_eeh_reset()
1065 phb = hose->private_data; in pnv_eeh_reset()
1066 if (phb->model == PNV_PHB_MODEL_P7IOC && in pnv_eeh_reset()
1069 rc = opal_pci_reset(phb->opal_id, in pnv_eeh_reset()
1075 return -EIO; in pnv_eeh_reset()
1079 if (pe->type & EEH_PE_VF) in pnv_eeh_reset()
1084 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", in pnv_eeh_reset()
1085 __func__, pe->phb->global_number, pe->addr); in pnv_eeh_reset()
1086 return -EIO; in pnv_eeh_reset()
1105 * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the in pnv_eeh_reset()
1106 * de-assert step. It's like the OPAL reset API was in pnv_eeh_reset()
1112 rc = pci_bus_error_reset(bus->self); in pnv_eeh_reset()
1118 if (pci_is_root_bus(bus->parent)) in pnv_eeh_reset()
1120 return pnv_eeh_bridge_reset(bus->self, option); in pnv_eeh_reset()
1124 * pnv_eeh_get_log - Retrieve error log
1136 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_log()
1142 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1155 * pnv_pe_err_inject - Inject specified error to the indicated PE
1169 struct pci_controller *hose = pe->phb; in pnv_eeh_err_inject()
1170 struct pnv_phb *phb = hose->private_data; in pnv_eeh_err_inject()
1177 return -ERANGE; in pnv_eeh_err_inject()
1184 return -ERANGE; in pnv_eeh_err_inject()
1191 return -ENXIO; in pnv_eeh_err_inject()
1195 rc = opal_pci_err_inject(phb->opal_id, pe->addr, in pnv_eeh_err_inject()
1199 "%d-%d to PHB#%x-PE#%x\n", in pnv_eeh_err_inject()
1201 hose->global_number, pe->addr); in pnv_eeh_err_inject()
1202 return -EIO; in pnv_eeh_err_inject()
1212 if (!edev || !edev->pe) in pnv_eeh_cfg_blocked()
1220 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) in pnv_eeh_cfg_blocked()
1223 if (edev->pe->state & EEH_PE_CFG_BLOCKED) in pnv_eeh_cfg_blocked()
1262 if (data->gemXfir || data->gemRfir || in pnv_eeh_dump_hub_diag_common()
1263 data->gemRirqfir || data->gemMask || data->gemRwof) in pnv_eeh_dump_hub_diag_common()
1265 be64_to_cpu(data->gemXfir), in pnv_eeh_dump_hub_diag_common()
1266 be64_to_cpu(data->gemRfir), in pnv_eeh_dump_hub_diag_common()
1267 be64_to_cpu(data->gemRirqfir), in pnv_eeh_dump_hub_diag_common()
1268 be64_to_cpu(data->gemMask), in pnv_eeh_dump_hub_diag_common()
1269 be64_to_cpu(data->gemRwof)); in pnv_eeh_dump_hub_diag_common()
1272 if (data->lemFir || data->lemErrMask || in pnv_eeh_dump_hub_diag_common()
1273 data->lemAction0 || data->lemAction1 || data->lemWof) in pnv_eeh_dump_hub_diag_common()
1275 be64_to_cpu(data->lemFir), in pnv_eeh_dump_hub_diag_common()
1276 be64_to_cpu(data->lemErrMask), in pnv_eeh_dump_hub_diag_common()
1277 be64_to_cpu(data->lemAction0), in pnv_eeh_dump_hub_diag_common()
1278 be64_to_cpu(data->lemAction1), in pnv_eeh_dump_hub_diag_common()
1279 be64_to_cpu(data->lemWof)); in pnv_eeh_dump_hub_diag_common()
1284 struct pnv_phb *phb = hose->private_data; in pnv_eeh_get_and_dump_hub_diag()
1286 (struct OpalIoP7IOCErrorData*)phb->diag_data; in pnv_eeh_get_and_dump_hub_diag()
1289 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); in pnv_eeh_get_and_dump_hub_diag()
1291 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", in pnv_eeh_get_and_dump_hub_diag()
1292 __func__, phb->hub_id, rc); in pnv_eeh_get_and_dump_hub_diag()
1296 switch (be16_to_cpu(data->type)) { in pnv_eeh_get_and_dump_hub_diag()
1298 pr_info("P7IOC diag-data for RGC\n\n"); in pnv_eeh_get_and_dump_hub_diag()
1300 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) in pnv_eeh_get_and_dump_hub_diag()
1302 be64_to_cpu(data->rgc.rgcStatus), in pnv_eeh_get_and_dump_hub_diag()
1303 be64_to_cpu(data->rgc.rgcLdcp)); in pnv_eeh_get_and_dump_hub_diag()
1306 pr_info("P7IOC diag-data for BI %s\n\n", in pnv_eeh_get_and_dump_hub_diag()
1307 data->bi.biDownbound ? "Downbound" : "Upbound"); in pnv_eeh_get_and_dump_hub_diag()
1309 if (data->bi.biLdcp0 || data->bi.biLdcp1 || in pnv_eeh_get_and_dump_hub_diag()
1310 data->bi.biLdcp2 || data->bi.biFenceStatus) in pnv_eeh_get_and_dump_hub_diag()
1312 be64_to_cpu(data->bi.biLdcp0), in pnv_eeh_get_and_dump_hub_diag()
1313 be64_to_cpu(data->bi.biLdcp1), in pnv_eeh_get_and_dump_hub_diag()
1314 be64_to_cpu(data->bi.biLdcp2), in pnv_eeh_get_and_dump_hub_diag()
1315 be64_to_cpu(data->bi.biFenceStatus)); in pnv_eeh_get_and_dump_hub_diag()
1318 pr_info("P7IOC diag-data for CI Port %d\n\n", in pnv_eeh_get_and_dump_hub_diag()
1319 data->ci.ciPort); in pnv_eeh_get_and_dump_hub_diag()
1321 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) in pnv_eeh_get_and_dump_hub_diag()
1323 be64_to_cpu(data->ci.ciPortStatus), in pnv_eeh_get_and_dump_hub_diag()
1324 be64_to_cpu(data->ci.ciPortLdcp)); in pnv_eeh_get_and_dump_hub_diag()
1327 pr_info("P7IOC diag-data for MISC\n\n"); in pnv_eeh_get_and_dump_hub_diag()
1331 pr_info("P7IOC diag-data for I2C\n\n"); in pnv_eeh_get_and_dump_hub_diag()
1335 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", in pnv_eeh_get_and_dump_hub_diag()
1336 __func__, phb->hub_id, data->type); in pnv_eeh_get_and_dump_hub_diag()
1343 struct pnv_phb *phb = hose->private_data; in pnv_eeh_get_pe()
1348 * If PHB supports compound PE, to fetch in pnv_eeh_get_pe()
1352 pnv_pe = &phb->ioda.pe_array[pe_no]; in pnv_eeh_get_pe()
1353 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { in pnv_eeh_get_pe()
1354 pnv_pe = pnv_pe->master; in pnv_eeh_get_pe()
1356 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); in pnv_eeh_get_pe()
1357 pe_no = pnv_pe->pe_number; in pnv_eeh_get_pe()
1363 return -EEXIST; in pnv_eeh_get_pe()
1365 /* Freeze the (compound) PE */ in pnv_eeh_get_pe()
1367 if (!(dev_pe->state & EEH_PE_ISOLATED)) in pnv_eeh_get_pe()
1368 phb->freeze_pe(phb, pe_no); in pnv_eeh_get_pe()
1371 * At this point, we're sure the (compound) PE should in pnv_eeh_get_pe()
1375 dev_pe = dev_pe->parent; in pnv_eeh_get_pe()
1376 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { in pnv_eeh_get_pe()
1378 ret = eeh_ops->get_state(dev_pe, NULL); in pnv_eeh_get_pe()
1380 dev_pe = dev_pe->parent; in pnv_eeh_get_pe()
1386 if (!(dev_pe->state & EEH_PE_ISOLATED)) in pnv_eeh_get_pe()
1387 phb->freeze_pe(phb, dev_pe->addr); in pnv_eeh_get_pe()
1390 dev_pe = dev_pe->parent; in pnv_eeh_get_pe()
1397 * pnv_eeh_next_error - Retrieve next EEH error to handle
1428 phb = hose->private_data; in pnv_eeh_next_error()
1430 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) in pnv_eeh_next_error()
1433 rc = opal_pci_next_error(phb->opal_id, in pnv_eeh_next_error()
1438 __func__, hose->global_number, rc); in pnv_eeh_next_error()
1446 __func__, hose->global_number); in pnv_eeh_next_error()
1458 hose->global_number); in pnv_eeh_next_error()
1477 hose->global_number, in pnv_eeh_next_error()
1485 hose->global_number, in pnv_eeh_next_error()
1491 hose->global_number, in pnv_eeh_next_error()
1494 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); in pnv_eeh_next_error()
1506 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", in pnv_eeh_next_error()
1507 hose->global_number, be64_to_cpu(frozen_pe_no)); in pnv_eeh_next_error()
1511 /* Dump PHB diag-data */ in pnv_eeh_next_error()
1512 rc = opal_pci_get_phb_diag_data2(phb->opal_id, in pnv_eeh_next_error()
1513 phb->diag_data, phb->diag_data_size); in pnv_eeh_next_error()
1516 phb->diag_data); in pnv_eeh_next_error()
1519 opal_pci_eeh_freeze_clear(phb->opal_id, in pnv_eeh_next_error()
1523 } else if ((*pe)->state & EEH_PE_ISOLATED || in pnv_eeh_next_error()
1529 (*pe)->addr, in pnv_eeh_next_error()
1530 (*pe)->phb->global_number); in pnv_eeh_next_error()
1553 !((*pe)->state & EEH_PE_ISOLATED)) { in pnv_eeh_next_error()
1558 pnv_pci_dump_phb_diag_data((*pe)->phb, in pnv_eeh_next_error()
1559 (*pe)->data); in pnv_eeh_next_error()
1567 parent_pe = (*pe)->parent; in pnv_eeh_next_error()
1570 if (parent_pe->type & EEH_PE_PHB) in pnv_eeh_next_error()
1574 state = eeh_ops->get_state(parent_pe, NULL); in pnv_eeh_next_error()
1579 parent_pe = parent_pe->parent; in pnv_eeh_next_error()
1609 return -EEXIST; in pnv_eeh_restore_config()
1611 if (edev->physfn) in pnv_eeh_restore_config()
1614 phb = edev->controller->private_data; in pnv_eeh_restore_config()
1615 ret = opal_pci_reinit(phb->opal_id, in pnv_eeh_restore_config()
1616 OPAL_REINIT_PCI_DEV, edev->bdfn); in pnv_eeh_restore_config()
1620 __func__, edev->bdfn, ret); in pnv_eeh_restore_config()
1621 return -EIO; in pnv_eeh_restore_config()
1644 * eeh_powernv_init - Register platform dependent EEH operations
1654 int ret = -EINVAL; in eeh_powernv_init()
1658 return -EINVAL; in eeh_powernv_init()
1670 phb = hose->private_data; in eeh_powernv_init()
1672 if (phb->model == PNV_PHB_MODEL_P7IOC) in eeh_powernv_init()
1675 if (phb->diag_data_size > max_diag_size) in eeh_powernv_init()
1676 max_diag_size = phb->diag_data_size; in eeh_powernv_init()