Lines Matching +full:pulse +full:- +full:code

33 #define PLB4OPB_GESR0		0x0	/* Error status 0: Master Dev 0-3 */
36 #define PLB4OPB_GESR1		0x4	/* Error Status 1: Master Dev 4-7 */
37 #define PLB4OPB_GESR2		0xC	/* Error Status 2: Master Dev 8-11 */
39 /* PLB4-to-AHB Bridge */
54 /* PLB4-to-PLB6 Bridge */
60 /* PLB6-to-PLB4 Bridge */
66 /* PLB6-to-MCIF Bridge */
164 /* PLB-Attached DDR3/4 Core Wrapper */
198 #define CMUN_URCR3_P		0x26 /* Unit Reset Control Reg 3 Pulse */
199 #define CMUN_PW0		0x2C /* Pulse Width Register */
200 #define CMUN_URCR0_P		0x2D /* Unit Reset Control Reg 0 Pulse */
201 #define CMUN_URCR1_P		0x2E /* Unit Reset Control Reg 1 Pulse */
202 #define CMUN_URCR2_P		0x2F /* Unit Reset Control Reg 2 Pulse */
203 #define CMUN_CLS_RW		0x30 /* Code Load Status (Read/Write) */
204 #define CMUN_CLS_S		0x31 /* Code Load Status (Set) */
205 #define CMUN_CLS_C		0x32 /* Code Load Status (Clear */