Lines Matching refs:r4
38 neg r6,r4
43 lbz r0,0(r4)
44 addi r4,r4,1
49 lhz r0,0(r4)
50 addi r4,r4,2
55 lwz r0,0(r4)
56 addi r4,r4,4
83 ld r0,0(r4)
84 ld r6,8(r4)
85 ld r7,16(r4)
86 ld r8,24(r4)
87 ld r9,32(r4)
88 ld r10,40(r4)
89 ld r11,48(r4)
90 ld r12,56(r4)
91 ld r14,64(r4)
92 ld r15,72(r4)
93 ld r16,80(r4)
94 ld r17,88(r4)
95 ld r18,96(r4)
96 ld r19,104(r4)
97 ld r20,112(r4)
98 ld r21,120(r4)
99 addi r4,r4,128
137 ld r0,0(r4)
138 ld r6,8(r4)
139 ld r7,16(r4)
140 ld r8,24(r4)
141 ld r9,32(r4)
142 ld r10,40(r4)
143 ld r11,48(r4)
144 ld r12,56(r4)
145 addi r4,r4,64
158 ld r0,0(r4)
159 ld r6,8(r4)
160 ld r7,16(r4)
161 ld r8,24(r4)
162 addi r4,r4,32
171 ld r0,0(r4)
172 ld r6,8(r4)
173 addi r4,r4,16
184 lwz r0,0(r4) /* Less chance of a reject with word ops */
185 lwz r6,4(r4)
186 addi r4,r4,8
192 lwz r0,0(r4)
193 addi r4,r4,4
198 lhz r0,0(r4)
199 addi r4,r4,2
204 lbz r0,0(r4)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
225 ld r4,STK_REG(R30)(r1)
234 clrrdi r6,r4,7
263 xor r6,r4,r3
273 lbz r0,0(r4)
274 addi r4,r4,1
279 lhz r0,0(r4)
280 addi r4,r4,2
285 lwz r0,0(r4)
286 addi r4,r4,4
291 ld r0,0(r4)
292 addi r4,r4,8
309 lvx v1,0,r4
310 addi r4,r4,16
315 lvx v1,0,r4
316 lvx v0,r4,r9
317 addi r4,r4,32
323 lvx v3,0,r4
324 lvx v2,r4,r9
325 lvx v1,r4,r10
326 lvx v0,r4,r11
327 addi r4,r4,64
354 lvx v7,0,r4
355 lvx v6,r4,r9
356 lvx v5,r4,r10
357 lvx v4,r4,r11
358 lvx v3,r4,r12
359 lvx v2,r4,r14
360 lvx v1,r4,r15
361 lvx v0,r4,r16
362 addi r4,r4,128
384 lvx v3,0,r4
385 lvx v2,r4,r9
386 lvx v1,r4,r10
387 lvx v0,r4,r11
388 addi r4,r4,64
396 lvx v1,0,r4
397 lvx v0,r4,r9
398 addi r4,r4,32
404 lvx v1,0,r4
405 addi r4,r4,16
413 ld r0,0(r4)
414 addi r4,r4,8
419 lwz r0,0(r4)
420 addi r4,r4,4
425 lhz r0,0(r4)
426 addi r4,r4,2
431 lbz r0,0(r4)
445 lbz r0,0(r4)
446 addi r4,r4,1
451 lhz r0,0(r4)
452 addi r4,r4,2
457 lwz r0,0(r4)
458 addi r4,r4,4
463 lwz r0,0(r4) /* Less chance of a reject with word ops */
464 lwz r7,4(r4)
465 addi r4,r4,8
482 LVS(v16,0,r4) /* Setup permute control vector */
483 lvx v0,0,r4
484 addi r4,r4,16
487 lvx v1,0,r4
489 addi r4,r4,16
495 lvx v1,0,r4
497 lvx v0,r4,r9
499 addi r4,r4,32
505 lvx v3,0,r4
507 lvx v2,r4,r9
509 lvx v1,r4,r10
511 lvx v0,r4,r11
513 addi r4,r4,64
540 lvx v7,0,r4
542 lvx v6,r4,r9
544 lvx v5,r4,r10
546 lvx v4,r4,r11
548 lvx v3,r4,r12
550 lvx v2,r4,r14
552 lvx v1,r4,r15
554 lvx v0,r4,r16
556 addi r4,r4,128
578 lvx v3,0,r4
580 lvx v2,r4,r9
582 lvx v1,r4,r10
584 lvx v0,r4,r11
586 addi r4,r4,64
594 lvx v1,0,r4
596 lvx v0,r4,r9
598 addi r4,r4,32
604 lvx v1,0,r4
606 addi r4,r4,16
612 addi r4,r4,-16 /* Unwind the +16 load offset */
615 lwz r0,0(r4) /* Less chance of a reject with word ops */
616 lwz r6,4(r4)
617 addi r4,r4,8
623 lwz r0,0(r4)
624 addi r4,r4,4
629 lhz r0,0(r4)
630 addi r4,r4,2
635 lbz r0,0(r4)