powerpc/kernel/head_40x.S

8  *      Low-level exception handers, MMU support, and rewrite.
82  * critical exception prolog.
102  * Exception prolog for critical exceptions.  This is a little different
103  * from the normal exception prolog above since a critical exception
104  * can potentially occur at any point during normal exception processing.
158 	stw	r9,_ESR(r11)		/* exception was taken		   */
171 	 *	now phys stack/exception frame pointer
180  * Exception vectors.
190  * 0x0100 - Critical Interrupt Exception
195  * 0x0200 - Machine Check Exception
200  * 0x0300 - Data Storage Exception
213  * 0x0400 - Instruction Storage Exception
225 /* 0x0500 - External Interrupt Exception */
226 	EXCEPTION(0x0500, HardwareInterrupt, do_IRQ)
228 /* 0x0600 - Alignment Exception */
236 /* 0x0700 - Program Exception */
244 	EXCEPTION(0x0800, Trap_08, unknown_exception)
245 	EXCEPTION(0x0900, Trap_09, unknown_exception)
246 	EXCEPTION(0x0A00, Trap_0A, unknown_exception)
247 	EXCEPTION(0x0B00, Trap_0B, unknown_exception)
249 /* 0x0C00 - System Call Exception */
252 /*	Trap_0D is commented out to get more space for system call exception */
254 /*	EXCEPTION(0x0D00, Trap_0D, unknown_exception) */
255 	EXCEPTION(0x0E00, Trap_0E, unknown_exception)
256 	EXCEPTION(0x0F00, Trap_0F, unknown_exception)
258 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
262 /* 0x1010 - Fixed Interval Timer (FIT) Exception */
266 /* 0x1020 - Watchdog Timer (WDT) Exception */
270 /* 0x1100 - Data TLB Miss Exception
344 	/* The bailout.  Restore registers to pre-exception conditions
355 /* 0x1200 - Instruction TLB Miss Exception
428 	/* The bailout.  Restore registers to pre-exception conditions
439 	EXCEPTION(0x1300, Trap_13, unknown_exception)
440 	EXCEPTION(0x1400, Trap_14, unknown_exception)
441 	EXCEPTION(0x1500, Trap_15, unknown_exception)
442 	EXCEPTION(0x1600, Trap_16, unknown_exception)
443 	EXCEPTION(0x1700, Trap_17, unknown_exception)
444 	EXCEPTION(0x1800, Trap_18, unknown_exception)
445 	EXCEPTION(0x1900, Trap_19, unknown_exception)
446 	EXCEPTION(0x1A00, Trap_1A, unknown_exception)
447 	EXCEPTION(0x1B00, Trap_1B, unknown_exception)
448 	EXCEPTION(0x1C00, Trap_1C, unknown_exception)
449 	EXCEPTION(0x1D00, Trap_1D, unknown_exception)
450 	EXCEPTION(0x1E00, Trap_1E, unknown_exception)
451 	EXCEPTION(0x1F00, Trap_1F, unknown_exception)
453 /* Check for a single step debug exception while in an exception
456  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
457  * the exception handler generates a single step debug exception.
459  * If we get a debug trap on the first instruction of an exception handler,
461  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
462  * The exception handler was handling a non-critical interrupt, so it will
466 	/* 0x2000 - Debug Exception */
471 	 * If this is a single step or branch-taken exception in an
472 	 * exception entry sequence, it was probably meant to apply to
473 	 * the code where the exception occurred (since exception entry
475 	 * of turning off DE on entry to an exception handler by turning
487 	bgt+    2f			/* address above exception vectors */
489 	/* here it looks like we got an inappropriate debug exception. */
507 	/* continue normal handling for a critical exception... */
514 	/* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
519 	mtspr	SPRN_TSR,r0		/* Clear the PIT exception */
524 	/* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
532 	/* Watchdog Timer (WDT) Exception. (from 0x1020) */
548 	 * exception space :-).  Both the instruction and data TLB
622  * and change to using our exception vectors.
708 	/* Establish the exception vector base