272 	 * of a prefetch, since if it is then the CPC sequencer may become  in cps_gen_flush_fsb()
391 	 * Load addresses of required CM & CPC registers. This is done early  in cps_gen_entry_code()
443 				/* Halt the VP via the CPC VP_STOP register */  in cps_gen_entry_code()
503 		/* Determine the CPC command to issue */  in cps_gen_entry_code()
516 		/* Issue the CPC command */  in cps_gen_entry_code()
535 		/* Barrier to ensure write to CPC command is complete */  in cps_gen_entry_code()
601 		 * power-up command to the CPC in order to resume operation.  in cps_gen_entry_code()
684 		 * of the cores, the JTAG detect bit indicates that the CPC will  in cps_pm_power_notifier()
720 	/* Detect whether a CPC is present */  in cps_pm_init()
726 			pr_warn("pm-cps: CPC does not support clock gating\n");  in cps_pm_init()
728 		/* Power gating is available with CPS SMP & any CPC */  in cps_pm_init()
734 		pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");  in cps_pm_init()