include/asm/mips-gic.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
29 /* For read-only shared registers */
31 	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
33 /* For read-write shared registers */
35 	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
37 /* For read-only local registers */
39 	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)	\
40 	CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
42 /* For read-write local registers */
44 	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)	\
45 	CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
47 /* For read-only shared per-interrupt registers */
60 /* For read-write shared per-interrupt registers */
71 /* For read-only local per-interrupt registers */
78 /* For read-write local per-interrupt registers */
85 /* For read-only shared bit-per-interrupt registers */
108 /* For read-write shared bit-per-interrupt registers */
149 /* For read-only local bit-per-interrupt registers */
156 /* For read-write local bit-per-interrupt registers */
163 /* GIC_SH_CONFIG - Information about the GIC configuration */
170 /* GIC_SH_COUNTER - Shared global counter value */
175 /* GIC_SH_POL_* - Configures interrupt polarity */
179 #define GIC_POL_FALLING_EDGE		0	/* when single-edge triggered */
180 #define GIC_POL_RISING_EDGE		1	/* when single-edge triggered */
182 /* GIC_SH_TRIG_* - Configures interrupts to be edge or level triggered */
187 /* GIC_SH_DUAL_* - Configures whether interrupts trigger on both edges */
189 #define GIC_DUAL_SINGLE			0	/* when edge-triggered */
190 #define GIC_DUAL_DUAL			1	/* when edge-triggered */
192 /* GIC_SH_WEDGE - Write an 'edge', ie. trigger an interrupt */
197 /* GIC_SH_RMASK_* - Reset/clear shared interrupt mask bits */
200 /* GIC_SH_SMASK_* - Set shared interrupt mask bits */
203 /* GIC_SH_MASK_* - Read the current shared interrupt mask */
206 /* GIC_SH_PEND_* - Read currently pending shared interrupts */
209 /* GIC_SH_MAPx_PIN - Map shared interrupts to a particular CPU pin */
215 /* GIC_SH_MAPx_VP - Map shared interrupts to a particular Virtual Processor */
218 /* GIC_Vx_CTL - VP-level interrupt control */
226 /* GIC_Vx_PEND - Read currently pending local interrupts */
229 /* GIC_Vx_MASK - Read the current local interrupt mask */
232 /* GIC_Vx_RMASK - Reset/clear local interrupt mask bits */
235 /* GIC_Vx_SMASK - Set local interrupt mask bits */
238 /* GIC_Vx_*_MAP - Route local interrupts to the desired pins */
241 /* GIC_Vx_WD_MAP - Route the local watchdog timer interrupt */
244 /* GIC_Vx_COMPARE_MAP - Route the local count/compare interrupt */
247 /* GIC_Vx_TIMER_MAP - Route the local CPU timer (cp0 count/compare) interrupt */
250 /* GIC_Vx_FDC_MAP - Route the local fast debug channel interrupt */
253 /* GIC_Vx_PERFCTR_MAP - Route the local performance counter interrupt */
256 /* GIC_Vx_SWINT0_MAP - Route the local software interrupt 0 */
259 /* GIC_Vx_SWINT1_MAP - Route the local software interrupt 1 */
262 /* GIC_Vx_OTHER - Configure access to other Virtual Processor registers */
266 /* GIC_Vx_IDENT - Retrieve the local Virtual Processor's ID */
270 /* GIC_Vx_COMPARE - Value to compare with GIC_SH_COUNTER */
273 /* GIC_Vx_EIC_SHADOW_SET_BASE - Set shadow register set for each interrupt */
277  * enum mips_gic_local_interrupt - GIC local interrupts
278  * @GIC_LOCAL_INT_WD: GIC watchdog timer interrupt
279  * @GIC_LOCAL_INT_COMPARE: GIC count/compare interrupt
287  * Enumerates interrupts provided by the GIC that are local to a VP.
301  * mips_gic_present() - Determine whether a GIC is present
303  * Determines whether a MIPS Global Interrupt Controller (GIC) is present in
306  * Return true if a GIC is present, else false.
314  * mips_gic_vx_map_reg() - Return GIC_Vx_<intr>_MAP register offset
315  * @intr: A GIC local interrupt
318  * within the block of GIC map registers. This is almost the same as the order
344  * gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq
347  * interrupt, which may be routed via the GIC.
354  * gic_get_c0_perfcount_int() - Return performance counter interrupt virq
357  * which may be routed via the GIC.
364  * gic_get_c0_fdc_int() - Return fast debug channel interrupt virq
367  * which may be routed via the GIC.