include/asm/mips-cm.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
18 /* The base address of the CM GCR block */
21 /* The base address of the CM L2-only sync region */
25  * __mips_cm_phys_base - retrieve the physical base address of the CM
27  * This function returns the physical base address of the Coherence Manager
37  * mips_cm_is64 - determine CM register width
40  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
41  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
42  * or vice-versa. This variable indicates the width of the memory accesses
46  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
51  * mips_cm_is_l2_hci_broken  - determine if HCI is broken
61  * mips_cm_error_report - Report CM cache errors
70  * mips_cm_probe - probe for a Coherence Manager
73  * is successfully detected, else -errno.
80 	return -ENODEV;  in mips_cm_probe()
85  * mips_cm_present - determine whether a Coherence Manager is present
99  * mips_cm_update_property - update property from the device tree
111  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
113  * Returns true if the system implements an L2-only sync region, else false.
124 /* Offsets to register blocks from the CM base address */
133 /* Size of the L2-only sync region */
152 /* GCR_CONFIG - Information about the system */
153 GCR_ACCESSOR_RO(64, 0x000, config)
160 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
161 GCR_ACCESSOR_RW(64, 0x008, base)
169 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
173 /* GCR_REV - Indicates the Coherence Manager revision */
187 /* GCR_ERR_CONTROL - Control error checking logic */
192 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
193 GCR_ACCESSOR_RW(64, 0x040, error_mask)
195 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
196 GCR_ACCESSOR_RW(64, 0x048, error_cause)
201 /* GCR_ERR_ADDR - Indicates the address associated with an error */
202 GCR_ACCESSOR_RW(64, 0x050, error_addr)
204 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
205 GCR_ACCESSOR_RW(64, 0x058, error_mult)
208 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
209 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
213 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
214 GCR_ACCESSOR_RW(64, 0x080, gic_base)
218 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
219 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
223 /* GCR_REGn_BASE - Base addresses of CM address regions */
224 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
225 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
226 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
227 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
230 /* GCR_REGn_MASK - Size & destination of CM address regions */
231 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
232 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
233 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
234 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
245 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
249 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
253 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
257 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
264 /* GCR_SYS_CONFIG2 - Further information about the system */
268 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
274 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
279 /* GCR_L2SM_COP - L2 cache op state machine control */
301 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
302 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
306 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
307 GCR_ACCESSOR_RW(64, 0x680, bev_base)
309 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
312 /* GCR_Cx_COHERENCE - Controls core coherence */
317 /* GCR_Cx_CONFIG - Information about a core's configuration */
322 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
337 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
341 /* GCR_Cx_ID - Identify the current core */
346 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
355  * mips_cm_l2sync - perform an L2-only sync operation
357  * If an L2-only sync region is present in the system then this function
358  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
363 		return -ENODEV;  in mips_cm_l2sync()
370  * mips_cm_revision() - return CM revision
384  * mips_cm_max_vp_width() - return the width in bits of VP indices
413  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
433  * mips_cm_lock_other - lock access to redirect/other region
446  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
454  * mips_cm_unlock_other - unlock access to redirect/other region
470  * mips_cm_lock_other_cpu - lock access to redirect/other region