903 	if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)  in get_pmu_evcntr()
920 	if (r->CRn == 9 && r->CRm == 13) {  in access_pmu_evcntr()
935 	} else if (r->CRn == 0 && r->CRm == 9) {  in access_pmu_evcntr()
941 	} else if (r->CRn == 14 && (r->CRm & 12) == 8) {  in access_pmu_evcntr()
975 	if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {  in access_pmu_evtyper()
979 	} else if (r->CRn == 14 && (r->CRm & 12) == 12) {  in access_pmu_evtyper()
1898 	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
2518 	{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2520 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },	      \
2522 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },	      \
2524 	{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2527 	{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
2536 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
2538 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
2542 	{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
2545 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
2547 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
2550 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
2552 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
2557 	{ Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
2559 	{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
2562 	{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
2574 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
2578 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
2581 	{ Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
2585 	{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
2588 	{ Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
2602 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
2605 	{ Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
2607 	{ Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
2609 	{ Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
2611 	{ Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
2613 	{ Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
2615 	{ Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
2629 	Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2),			\
2649 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
2650 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
2652 	{ AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
2654 	{ AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
2655 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2656 	{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2658 	{ AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2660 	{ AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2661 	{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2663 	{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2664 	{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2666 	{ Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2668 	{ Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2670 	{ AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2672 	{ AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2677 	{ Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2678 	{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2679 	{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2703 	{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2705 	{ AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2707 	{ AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2709 	{ AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2712 	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2714 	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2787 	{ Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2788 	{ Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2791 	{ Op1(1), CRn( 0), CRm( 0),  Op2(2), undef_access },
2793 	{ Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2797 	{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2799 	{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2801 	{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2802 	{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2803 	{ Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2934 	params.CRn = 0;  in kvm_handle_cp_64()
2979 	params->CRn = 0;  in kvm_esr_cp10_id_to_sys64()
3122 	if (params.Op1 == 0 && params.CRn == 0 && params.CRm)  in kvm_handle_cp15_32()
3145 	return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;  in is_imp_def_sys_reg()
3271 		params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)  in index_to_params()
3545 		(reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |  in sys_reg_to_index()