dts/ti/k3-j7200-som-p0.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200.dtsi"
18 	reserved_memory: reserved-memory {
19 		#address-cells = <2>;
20 		#size-cells = <2>;
26 			no-map;
29 		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30 			compatible = "shared-dma-pool";
32 			no-map;
35 		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
36 			compatible = "shared-dma-pool";
38 			no-map;
41 		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
42 			compatible = "shared-dma-pool";
44 			no-map;
47 		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
48 			compatible = "shared-dma-pool";
50 			no-map;
53 		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
54 			compatible = "shared-dma-pool";
56 			no-map;
59 		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
60 			compatible = "shared-dma-pool";
62 			no-map;
65 		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
66 			compatible = "shared-dma-pool";
68 			no-map;
71 		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
72 			compatible = "shared-dma-pool";
74 			no-map;
77 		rtos_ipc_memory_region: ipc-memories@a4000000 {
80 			no-map;
86 	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
87 		pinctrl-single,pins = <
104 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
105 		pinctrl-single,pins = <
122 	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
123 			pinctrl-single,pins = <
131 	main_i2c0_pins_default: main-i2c0-default-pins {
132 		pinctrl-single,pins = <
144 	pinctrl-names = "default";
145 	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
146 	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
149 	flash@0,0 {
150 		compatible = "cypress,hyperflash", "cfi-flash";
154 			compatible = "fixed-partitions";
155 			#address-cells = <1>;
156 			#size-cells = <1>;
169 				label = "hbmc.u-boot";
190 	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
191 		ti,mbox-rx = <0 0 0>;
192 		ti,mbox-tx = <1 0 0>;
195 	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
196 		ti,mbox-rx = <2 0 0>;
197 		ti,mbox-tx = <3 0 0>;
205 	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
206 		ti,mbox-rx = <0 0 0>;
207 		ti,mbox-tx = <1 0 0>;
210 	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
211 		ti,mbox-rx = <2 0 0>;
212 		ti,mbox-tx = <3 0 0>;
218 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
224 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
230 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
236 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
241 	pinctrl-names = "default";
242 	pinctrl-0 = <&main_i2c0_pins_default>;
243 	clock-frequency = <400000>;
248 		gpio-controller;
249 		#gpio-cells = <2>;
250 		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
259 	pinctrl-names = "default";
260 	pinctrl-0 = <&wkup_i2c0_pins_default>;
261 	clock-frequency = <400000>;
271 	pinctrl-names = "default";
272 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
274 	flash@0 {
275 		compatible = "jedec,spi-nor";
277 		spi-tx-bus-width = <8>;
278 		spi-rx-bus-width = <8>;
279 		spi-max-frequency = <25000000>;
280 		cdns,tshsl-ns = <60>;
281 		cdns,tsd2d-ns = <60>;
282 		cdns,tchsh-ns = <60>;
283 		cdns,tslch-ns = <60>;
284 		cdns,read-delay = <4>;
287 			compatible = "fixed-partitions";
288 			#address-cells = <1>;
289 			#size-cells = <1>;
302 				label = "ospi.u-boot";