Lines Matching +full:sdm845 +full:- +full:rpmhpd
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
44 bi_tcxo_div2: bi-tcxo-div2-clk {
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
48 clock-mult = <1>;
49 clock-div = <2>;
52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
53 #clock-cells = <0>;
54 compatible = "fixed-factor-clock";
56 clock-mult = <1>;
57 clock-div = <2>;
60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
67 #address-cells = <2>;
68 #size-cells = <0>;
72 compatible = "arm,cortex-a510";
75 enable-method = "psci";
76 next-level-cache = <&L2_0>;
77 power-domains = <&CPU_PD0>;
78 power-domain-names = "psci";
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 capacity-dmips-mhz = <1024>;
81 dynamic-power-coefficient = <100>;
82 #cooling-cells = <2>;
83 L2_0: l2-cache {
85 cache-level = <2>;
86 cache-unified;
87 next-level-cache = <&L3_0>;
88 L3_0: l3-cache {
90 cache-level = <3>;
91 cache-unified;
98 compatible = "arm,cortex-a510";
101 enable-method = "psci";
102 next-level-cache = <&L2_100>;
103 power-domains = <&CPU_PD1>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 capacity-dmips-mhz = <1024>;
107 dynamic-power-coefficient = <100>;
108 #cooling-cells = <2>;
109 L2_100: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
119 compatible = "arm,cortex-a510";
122 enable-method = "psci";
123 next-level-cache = <&L2_200>;
124 power-domains = <&CPU_PD2>;
125 power-domain-names = "psci";
126 qcom,freq-domain = <&cpufreq_hw 0>;
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
129 #cooling-cells = <2>;
130 L2_200: l2-cache {
132 cache-level = <2>;
133 cache-unified;
134 next-level-cache = <&L3_0>;
140 compatible = "arm,cortex-a715";
143 enable-method = "psci";
144 next-level-cache = <&L2_300>;
145 power-domains = <&CPU_PD3>;
146 power-domain-names = "psci";
147 qcom,freq-domain = <&cpufreq_hw 1>;
148 capacity-dmips-mhz = <1792>;
149 dynamic-power-coefficient = <270>;
150 #cooling-cells = <2>;
151 L2_300: l2-cache {
153 cache-level = <2>;
154 cache-unified;
155 next-level-cache = <&L3_0>;
161 compatible = "arm,cortex-a715";
164 enable-method = "psci";
165 next-level-cache = <&L2_400>;
166 power-domains = <&CPU_PD4>;
167 power-domain-names = "psci";
168 qcom,freq-domain = <&cpufreq_hw 1>;
169 capacity-dmips-mhz = <1792>;
170 dynamic-power-coefficient = <270>;
171 #cooling-cells = <2>;
172 L2_400: l2-cache {
174 cache-level = <2>;
175 cache-unified;
176 next-level-cache = <&L3_0>;
182 compatible = "arm,cortex-a710";
185 enable-method = "psci";
186 next-level-cache = <&L2_500>;
187 power-domains = <&CPU_PD5>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 1>;
190 capacity-dmips-mhz = <1792>;
191 dynamic-power-coefficient = <270>;
192 #cooling-cells = <2>;
193 L2_500: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&L3_0>;
203 compatible = "arm,cortex-a710";
206 enable-method = "psci";
207 next-level-cache = <&L2_600>;
208 power-domains = <&CPU_PD6>;
209 power-domain-names = "psci";
210 qcom,freq-domain = <&cpufreq_hw 1>;
211 capacity-dmips-mhz = <1792>;
212 dynamic-power-coefficient = <270>;
213 #cooling-cells = <2>;
214 L2_600: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&L3_0>;
224 compatible = "arm,cortex-x3";
227 enable-method = "psci";
228 next-level-cache = <&L2_700>;
229 power-domains = <&CPU_PD7>;
230 power-domain-names = "psci";
231 qcom,freq-domain = <&cpufreq_hw 2>;
232 capacity-dmips-mhz = <1894>;
233 dynamic-power-coefficient = <588>;
234 #cooling-cells = <2>;
235 L2_700: l2-cache {
237 cache-level = <2>;
238 cache-unified;
239 next-level-cache = <&L3_0>;
243 cpu-map {
279 idle-states {
280 entry-method = "psci";
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "silver-rail-power-collapse";
285 arm,psci-suspend-param = <0x40000004>;
286 entry-latency-us = <550>;
287 exit-latency-us = <750>;
288 min-residency-us = <6700>;
289 local-timer-stop;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "gold-rail-power-collapse";
295 arm,psci-suspend-param = <0x40000004>;
296 entry-latency-us = <600>;
297 exit-latency-us = <1300>;
298 min-residency-us = <8136>;
299 local-timer-stop;
302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
303 compatible = "arm,idle-state";
304 idle-state-name = "goldplus-rail-power-collapse";
305 arm,psci-suspend-param = <0x40000004>;
306 entry-latency-us = <500>;
307 exit-latency-us = <1350>;
308 min-residency-us = <7480>;
309 local-timer-stop;
313 domain-idle-states {
314 CLUSTER_SLEEP_0: cluster-sleep-0 {
315 compatible = "domain-idle-state";
316 arm,psci-suspend-param = <0x41000044>;
317 entry-latency-us = <750>;
318 exit-latency-us = <2350>;
319 min-residency-us = <9144>;
322 CLUSTER_SLEEP_1: cluster-sleep-1 {
323 compatible = "domain-idle-state";
324 arm,psci-suspend-param = <0x4100c344>;
325 entry-latency-us = <2800>;
326 exit-latency-us = <4400>;
327 min-residency-us = <10150>;
334 compatible = "qcom,scm-sm8550", "qcom,scm";
339 clk_virt: interconnect-0 {
340 compatible = "qcom,sm8550-clk-virt";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
345 mc_virt: interconnect-1 {
346 compatible = "qcom,sm8550-mc-virt";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
358 compatible = "arm,armv8-pmuv3";
363 compatible = "arm,psci-1.0";
366 CPU_PD0: power-domain-cpu0 {
367 #power-domain-cells = <0>;
368 power-domains = <&CLUSTER_PD>;
369 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
372 CPU_PD1: power-domain-cpu1 {
373 #power-domain-cells = <0>;
374 power-domains = <&CLUSTER_PD>;
375 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
378 CPU_PD2: power-domain-cpu2 {
379 #power-domain-cells = <0>;
380 power-domains = <&CLUSTER_PD>;
381 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
384 CPU_PD3: power-domain-cpu3 {
385 #power-domain-cells = <0>;
386 power-domains = <&CLUSTER_PD>;
387 domain-idle-states = <&BIG_CPU_SLEEP_0>;
390 CPU_PD4: power-domain-cpu4 {
391 #power-domain-cells = <0>;
392 power-domains = <&CLUSTER_PD>;
393 domain-idle-states = <&BIG_CPU_SLEEP_0>;
396 CPU_PD5: power-domain-cpu5 {
397 #power-domain-cells = <0>;
398 power-domains = <&CLUSTER_PD>;
399 domain-idle-states = <&BIG_CPU_SLEEP_0>;
402 CPU_PD6: power-domain-cpu6 {
403 #power-domain-cells = <0>;
404 power-domains = <&CLUSTER_PD>;
405 domain-idle-states = <&BIG_CPU_SLEEP_0>;
408 CPU_PD7: power-domain-cpu7 {
409 #power-domain-cells = <0>;
410 power-domains = <&CLUSTER_PD>;
411 domain-idle-states = <&PRIME_CPU_SLEEP_0>;
414 CLUSTER_PD: power-domain-cluster {
415 #power-domain-cells = <0>;
416 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
420 reserved_memory: reserved-memory {
421 #address-cells = <2>;
422 #size-cells = <2>;
425 hyp_mem: hyp-region@80000000 {
427 no-map;
430 cpusys_vm_mem: cpusys-vm-region@80a00000 {
432 no-map;
435 hyp_tags_mem: hyp-tags-region@80e00000 {
437 no-map;
440 xbl_sc_mem: xbl-sc-region@d8100000 {
442 no-map;
445 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
447 no-map;
451 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
453 no-map;
456 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
457 compatible = "qcom,cmd-db";
459 no-map;
463 aop_config_merged_mem: aop-config-merged-region@81c80000 {
465 no-map;
473 no-map;
476 adsp_mhi_mem: adsp-mhi-region@81f00000 {
478 no-map;
481 global_sync_mem: global-sync-region@82600000 {
483 no-map;
486 tz_stat_mem: tz-stat-region@82700000 {
488 no-map;
491 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
493 no-map;
496 mpss_mem: mpss-region@8a800000 {
498 no-map;
501 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
503 no-map;
506 ipa_fw_mem: ipa-fw-region@9b080000 {
508 no-map;
511 ipa_gsi_mem: ipa-gsi-region@9b090000 {
513 no-map;
516 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
518 no-map;
521 spss_region_mem: spss-region@9b100000 {
523 no-map;
527 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
529 no-map;
533 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
535 no-map;
538 camera_mem: camera-region@9b300000 {
540 no-map;
543 video_mem: video-region@9bb00000 {
545 no-map;
548 cvp_mem: cvp-region@9c200000 {
550 no-map;
553 cdsp_mem: cdsp-region@9c900000 {
555 no-map;
558 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
560 no-map;
563 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
565 no-map;
568 adspslpi_mem: adspslpi-region@9ea00000 {
570 no-map;
577 rmtfs_mem: rmtfs-region@d4a80000 {
578 compatible = "qcom,rmtfs-mem";
580 no-map;
582 qcom,client-id = <1>;
586 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
588 no-map;
591 tz_reserved_mem: tz-reserved-region@d8000000 {
593 no-map;
596 cpucp_fw_mem: cpucp-fw-region@d8140000 {
598 no-map;
601 qtee_mem: qtee-region@d8300000 {
603 no-map;
606 ta_mem: ta-region@d8800000 {
608 no-map;
611 tz_tags_mem: tz-tags-region@e1200000 {
613 no-map;
616 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
618 no-map;
621 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
623 no-map;
626 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
628 no-map;
631 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
633 no-map;
636 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
638 no-map;
641 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
643 no-map;
646 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
648 no-map;
651 oem_vm_mem: oem-vm-region@f8400000 {
653 no-map;
656 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
658 no-map;
661 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
663 no-map;
666 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
668 no-map;
671 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
673 no-map;
677 smp2p-adsp {
680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
686 qcom,local-pid = <0>;
687 qcom,remote-pid = <2>;
689 smp2p_adsp_out: master-kernel {
690 qcom,entry-name = "master-kernel";
691 #qcom,smem-state-cells = <1>;
694 smp2p_adsp_in: slave-kernel {
695 qcom,entry-name = "slave-kernel";
696 interrupt-controller;
697 #interrupt-cells = <2>;
701 smp2p-cdsp {
704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
710 qcom,local-pid = <0>;
711 qcom,remote-pid = <5>;
713 smp2p_cdsp_out: master-kernel {
714 qcom,entry-name = "master-kernel";
715 #qcom,smem-state-cells = <1>;
718 smp2p_cdsp_in: slave-kernel {
719 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 smp2p-modem {
728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <1>;
737 smp2p_modem_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 smp2p_modem_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
748 ipa_smp2p_out: ipa-ap-to-modem {
749 qcom,entry-name = "ipa";
750 #qcom,smem-state-cells = <1>;
753 ipa_smp2p_in: ipa-modem-to-ap {
754 qcom,entry-name = "ipa";
755 interrupt-controller;
756 #interrupt-cells = <2>;
761 compatible = "simple-bus";
763 dma-ranges = <0 0 0 0 0x10 0>;
765 #address-cells = <2>;
766 #size-cells = <2>;
768 gcc: clock-controller@100000 {
769 compatible = "qcom,sm8550-gcc";
771 #clock-cells = <1>;
772 #reset-cells = <1>;
773 #power-domain-cells = <1>;
785 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
788 interrupt-controller;
789 #interrupt-cells = <3>;
790 #mbox-cells = <2>;
793 gpi_dma2: dma-controller@800000 {
794 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
795 #dma-cells = <3>;
809 dma-channels = <12>;
810 dma-channel-mask = <0x3e>;
816 compatible = "qcom,geni-se-qup";
819 clock-names = "m-ahb", "s-ahb";
823 #address-cells = <2>;
824 #size-cells = <2>;
828 compatible = "qcom,geni-i2c";
830 clock-names = "se";
832 pinctrl-names = "default";
833 pinctrl-0 = <&qup_i2c8_data_clk>;
835 #address-cells = <1>;
836 #size-cells = <0>;
840 interconnect-names = "qup-core", "qup-config", "qup-memory";
843 dma-names = "tx", "rx";
848 compatible = "qcom,geni-spi";
850 clock-names = "se";
853 pinctrl-names = "default";
854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
858 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dma-names = "tx", "rx";
862 #address-cells = <1>;
863 #size-cells = <0>;
868 compatible = "qcom,geni-i2c";
870 clock-names = "se";
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_i2c9_data_clk>;
875 #address-cells = <1>;
876 #size-cells = <0>;
880 interconnect-names = "qup-core", "qup-config", "qup-memory";
883 dma-names = "tx", "rx";
888 compatible = "qcom,geni-spi";
890 clock-names = "se";
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
898 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 dma-names = "tx", "rx";
902 #address-cells = <1>;
903 #size-cells = <0>;
908 compatible = "qcom,geni-i2c";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_i2c10_data_clk>;
915 #address-cells = <1>;
916 #size-cells = <0>;
920 interconnect-names = "qup-core", "qup-config", "qup-memory";
923 dma-names = "tx", "rx";
928 compatible = "qcom,geni-spi";
930 clock-names = "se";
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
941 dma-names = "tx", "rx";
942 #address-cells = <1>;
943 #size-cells = <0>;
948 compatible = "qcom,geni-i2c";
950 clock-names = "se";
952 pinctrl-names = "default";
953 pinctrl-0 = <&qup_i2c11_data_clk>;
955 #address-cells = <1>;
956 #size-cells = <0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
963 dma-names = "tx", "rx";
968 compatible = "qcom,geni-spi";
970 clock-names = "se";
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
978 interconnect-names = "qup-core", "qup-config", "qup-memory";
981 dma-names = "tx", "rx";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c12_data_clk>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1003 dma-names = "tx", "rx";
1008 compatible = "qcom,geni-spi";
1010 clock-names = "se";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1018 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 dma-names = "tx", "rx";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-i2c";
1030 clock-names = "se";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_i2c13_data_clk>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1040 interconnect-names = "qup-core", "qup-config", "qup-memory";
1043 dma-names = "tx", "rx";
1048 compatible = "qcom,geni-spi";
1050 clock-names = "se";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1058 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 dma-names = "tx", "rx";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c15_data_clk>;
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1083 dma-names = "tx", "rx";
1088 compatible = "qcom,geni-spi";
1090 clock-names = "se";
1093 pinctrl-names = "default";
1094 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1098 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 dma-names = "tx", "rx";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1109 compatible = "qcom,geni-se-i2c-master-hub";
1111 clock-names = "s-ahb";
1113 #address-cells = <2>;
1114 #size-cells = <2>;
1119 compatible = "qcom,geni-i2c-master-hub";
1121 clock-names = "se", "core";
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&hub_i2c0_data_clk>;
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1131 interconnect-names = "qup-core", "qup-config";
1136 compatible = "qcom,geni-i2c-master-hub";
1138 clock-names = "se", "core";
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&hub_i2c1_data_clk>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1148 interconnect-names = "qup-core", "qup-config";
1153 compatible = "qcom,geni-i2c-master-hub";
1155 clock-names = "se", "core";
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&hub_i2c2_data_clk>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1165 interconnect-names = "qup-core", "qup-config";
1170 compatible = "qcom,geni-i2c-master-hub";
1172 clock-names = "se", "core";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&hub_i2c3_data_clk>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1182 interconnect-names = "qup-core", "qup-config";
1187 compatible = "qcom,geni-i2c-master-hub";
1189 clock-names = "se", "core";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&hub_i2c4_data_clk>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1199 interconnect-names = "qup-core", "qup-config";
1204 compatible = "qcom,geni-i2c-master-hub";
1206 clock-names = "se", "core";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&hub_i2c5_data_clk>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1216 interconnect-names = "qup-core", "qup-config";
1221 compatible = "qcom,geni-i2c-master-hub";
1223 clock-names = "se", "core";
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&hub_i2c6_data_clk>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1233 interconnect-names = "qup-core", "qup-config";
1238 compatible = "qcom,geni-i2c-master-hub";
1240 clock-names = "se", "core";
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&hub_i2c7_data_clk>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1250 interconnect-names = "qup-core", "qup-config";
1255 compatible = "qcom,geni-i2c-master-hub";
1257 clock-names = "se", "core";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&hub_i2c8_data_clk>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1267 interconnect-names = "qup-core", "qup-config";
1272 compatible = "qcom,geni-i2c-master-hub";
1274 clock-names = "se", "core";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&hub_i2c9_data_clk>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1284 interconnect-names = "qup-core", "qup-config";
1289 gpi_dma1: dma-controller@a00000 {
1290 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1291 #dma-cells = <3>;
1305 dma-channels = <12>;
1306 dma-channel-mask = <0x1e>;
1312 compatible = "qcom,geni-se-qup";
1315 clock-names = "m-ahb", "s-ahb";
1320 interconnect-names = "qup-core";
1321 #address-cells = <2>;
1322 #size-cells = <2>;
1326 compatible = "qcom,geni-i2c";
1328 clock-names = "se";
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&qup_i2c0_data_clk>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1338 interconnect-names = "qup-core", "qup-config", "qup-memory";
1341 dma-names = "tx", "rx";
1346 compatible = "qcom,geni-spi";
1348 clock-names = "se";
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1356 interconnect-names = "qup-core", "qup-config", "qup-memory";
1359 dma-names = "tx", "rx";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "qcom,geni-i2c";
1368 clock-names = "se";
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_i2c1_data_clk>;
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1378 interconnect-names = "qup-core", "qup-config", "qup-memory";
1381 dma-names = "tx", "rx";
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1396 interconnect-names = "qup-core", "qup-config", "qup-memory";
1399 dma-names = "tx", "rx";
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1406 compatible = "qcom,geni-i2c";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c2_data_clk>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1421 dma-names = "tx", "rx";
1426 compatible = "qcom,geni-spi";
1428 clock-names = "se";
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1436 interconnect-names = "qup-core", "qup-config", "qup-memory";
1439 dma-names = "tx", "rx";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 dma-names = "tx", "rx";
1466 compatible = "qcom,geni-spi";
1468 clock-names = "se";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1479 dma-names = "tx", "rx";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1486 compatible = "qcom,geni-i2c";
1488 clock-names = "se";
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 dma-names = "tx", "rx";
1506 compatible = "qcom,geni-spi";
1508 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1516 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 dma-names = "tx", "rx";
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1526 compatible = "qcom,geni-i2c";
1528 clock-names = "se";
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_i2c5_data_clk>;
1536 interconnect-names = "qup-core", "qup-config", "qup-memory";
1539 dma-names = "tx", "rx";
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-spi";
1548 clock-names = "se";
1551 pinctrl-names = "default";
1552 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1559 dma-names = "tx", "rx";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1566 compatible = "qcom,geni-i2c";
1568 clock-names = "se";
1570 pinctrl-names = "default";
1571 pinctrl-0 = <&qup_i2c6_data_clk>;
1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 dma-names = "tx", "rx";
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1586 compatible = "qcom,geni-spi";
1588 clock-names = "se";
1591 pinctrl-names = "default";
1592 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1596 interconnect-names = "qup-core", "qup-config", "qup-memory";
1599 dma-names = "tx", "rx";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 compatible = "qcom,geni-debug-uart";
1608 clock-names = "se";
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&qup_uart7_default>;
1613 interconnect-names = "qup-core", "qup-config";
1621 compatible = "qcom,sm8550-cnoc-main";
1623 #interconnect-cells = <2>;
1624 qcom,bcm-voters = <&apps_bcm_voter>;
1628 compatible = "qcom,sm8550-config-noc";
1630 #interconnect-cells = <2>;
1631 qcom,bcm-voters = <&apps_bcm_voter>;
1635 compatible = "qcom,sm8550-system-noc";
1637 #interconnect-cells = <2>;
1638 qcom,bcm-voters = <&apps_bcm_voter>;
1642 compatible = "qcom,sm8550-pcie-anoc";
1644 #interconnect-cells = <2>;
1647 qcom,bcm-voters = <&apps_bcm_voter>;
1651 compatible = "qcom,sm8550-aggre1-noc";
1653 #interconnect-cells = <2>;
1656 qcom,bcm-voters = <&apps_bcm_voter>;
1660 compatible = "qcom,sm8550-aggre2-noc";
1662 #interconnect-cells = <2>;
1664 qcom,bcm-voters = <&apps_bcm_voter>;
1668 compatible = "qcom,sm8550-mmss-noc";
1670 #interconnect-cells = <2>;
1671 qcom,bcm-voters = <&apps_bcm_voter>;
1676 compatible = "qcom,pcie-sm8550";
1682 reg-names = "parf", "dbi", "elbi", "atu", "config";
1683 #address-cells = <3>;
1684 #size-cells = <2>;
1687 bus-range = <0x00 0xff>;
1689 dma-coherent;
1691 linux,pci-domain = <0>;
1692 num-lanes = <2>;
1695 interrupt-names = "msi";
1697 #interrupt-cells = <1>;
1698 interrupt-map-mask = <0 0 0 0x7>;
1699 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1711 clock-names = "aux",
1721 interconnect-names = "pcie-mem", "cpu-pcie";
1723 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1727 reset-names = "pci";
1729 power-domains = <&gcc PCIE_0_GDSC>;
1732 phy-names = "pciephy";
1738 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1746 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1750 reset-names = "phy";
1752 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1753 assigned-clock-rates = <100000000>;
1755 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1757 #clock-cells = <0>;
1758 clock-output-names = "pcie0_pipe_clk";
1760 #phy-cells = <0>;
1767 compatible = "qcom,pcie-sm8550";
1773 reg-names = "parf", "dbi", "elbi", "atu", "config";
1774 #address-cells = <3>;
1775 #size-cells = <2>;
1778 bus-range = <0x00 0xff>;
1780 dma-coherent;
1782 linux,pci-domain = <1>;
1783 num-lanes = <2>;
1786 interrupt-names = "msi";
1788 #interrupt-cells = <1>;
1789 interrupt-map-mask = <0 0 0 0x7>;
1790 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1803 clock-names = "aux",
1812 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1813 assigned-clock-rates = <19200000>;
1817 interconnect-names = "pcie-mem", "cpu-pcie";
1819 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1824 reset-names = "pci", "link_down";
1826 power-domains = <&gcc PCIE_1_GDSC>;
1829 phy-names = "pciephy";
1835 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1843 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1848 reset-names = "phy", "phy_nocsr";
1850 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1851 assigned-clock-rates = <100000000>;
1853 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1855 #clock-cells = <0>;
1856 clock-output-names = "pcie1_pipe_clk";
1858 #phy-cells = <0>;
1863 cryptobam: dma-controller@1dc4000 {
1864 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1867 #dma-cells = <1>;
1869 qcom,controlled-remotely;
1875 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1878 dma-names = "rx", "tx";
1882 interconnect-names = "memory";
1886 compatible = "qcom,sm8550-qmp-ufs-phy";
1890 clock-names = "ref", "ref_aux";
1892 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1895 reset-names = "ufsphy";
1897 #clock-cells = <1>;
1898 #phy-cells = <0>;
1904 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1905 "jedec,ufs-2.0";
1909 phy-names = "ufsphy";
1910 lanes-per-direction = <2>;
1911 #reset-cells = <1>;
1913 reset-names = "rst";
1915 power-domains = <&gcc UFS_PHY_GDSC>;
1916 required-opps = <&rpmhpd_opp_nom>;
1919 dma-coherent;
1924 interconnect-names = "ufs-ddr", "cpu-ufs";
1925 clock-names = "core_clk",
1941 freq-table-hz =
1956 compatible = "qcom,sm8550-inline-crypto-engine",
1957 "qcom,inline-crypto-engine";
1963 compatible = "qcom,tcsr-mutex";
1965 #hwlock-cells = <1>;
1968 tcsr: clock-controller@1fc0000 {
1969 compatible = "qcom,sm8550-tcsr", "syscon";
1972 #clock-cells = <1>;
1973 #reset-cells = <1>;
1976 gpucc: clock-controller@3d90000 {
1977 compatible = "qcom,sm8550-gpucc";
1982 #clock-cells = <1>;
1983 #reset-cells = <1>;
1984 #power-domain-cells = <1>;
1988 compatible = "qcom,sm8550-mpss-pas";
1991 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
1997 interrupt-names = "wdog", "fatal", "ready", "handover",
1998 "stop-ack", "shutdown-ack";
2001 clock-names = "xo";
2003 power-domains = <&rpmhpd RPMHPD_CX>,
2004 <&rpmhpd RPMHPD_MSS>;
2005 power-domain-names = "cx", "mss";
2009 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2013 qcom,smem-states = <&smp2p_modem_out 0>;
2014 qcom,smem-state-names = "stop";
2018 glink-edge {
2019 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2025 qcom,remote-pid = <1>;
2030 compatible = "qcom,sm8550-adsp-pas";
2033 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2038 interrupt-names = "wdog", "fatal", "ready",
2039 "handover", "stop-ack";
2042 clock-names = "xo";
2044 power-domains = <&rpmhpd RPMHPD_LCX>,
2045 <&rpmhpd RPMHPD_LMX>;
2046 power-domain-names = "lcx", "lmx";
2050 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2054 qcom,smem-states = <&smp2p_adsp_out 0>;
2055 qcom,smem-state-names = "stop";
2059 remoteproc_adsp_glink: glink-edge {
2060 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2067 qcom,remote-pid = <2>;
2071 qcom,glink-channels = "fastrpcglink-apps-dsp";
2073 qcom,non-secure-domain;
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2077 compute-cb@3 {
2078 compatible = "qcom,fastrpc-compute-cb";
2082 dma-coherent;
2085 compute-cb@4 {
2086 compatible = "qcom,fastrpc-compute-cb";
2090 dma-coherent;
2093 compute-cb@5 {
2094 compatible = "qcom,fastrpc-compute-cb";
2098 dma-coherent;
2101 compute-cb@6 {
2102 compatible = "qcom,fastrpc-compute-cb";
2106 dma-coherent;
2109 compute-cb@7 {
2110 compatible = "qcom,fastrpc-compute-cb";
2114 dma-coherent;
2120 qcom,glink-channels = "adsp_apps";
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2129 #sound-dai-cells = <0>;
2130 qcom,protection-domain = "avs/audio",
2134 compatible = "qcom,q6apm-dais";
2140 compatible = "qcom,q6apm-lpass-dais";
2141 #sound-dai-cells = <1>;
2148 qcom,protection-domain = "avs/audio",
2151 q6prmcc: clock-controller {
2152 compatible = "qcom,q6prm-lpass-clocks";
2153 #clock-cells = <2>;
2161 compatible = "qcom,sm8550-lpass-wsa-macro";
2167 clock-names = "mclk", "macro", "dcodec", "fsgen";
2168 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2169 assigned-clock-rates = <19200000>;
2171 #clock-cells = <0>;
2172 clock-output-names = "wsa2-mclk";
2173 pinctrl-names = "default";
2174 pinctrl-0 = <&wsa2_swr_active>;
2175 #sound-dai-cells = <1>;
2179 compatible = "qcom,soundwire-v2.0.0";
2183 clock-names = "iface";
2186 qcom,din-ports = <4>;
2187 qcom,dout-ports = <9>;
2189 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2190 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2191 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2192 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2193 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2194 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2195 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2196 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2197 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2199 #address-cells = <2>;
2200 #size-cells = <0>;
2201 #sound-dai-cells = <1>;
2206 compatible = "qcom,sm8550-lpass-rx-macro";
2212 clock-names = "mclk", "macro", "dcodec", "fsgen";
2214 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2215 assigned-clock-rates = <19200000>;
2217 #clock-cells = <0>;
2218 clock-output-names = "mclk";
2219 pinctrl-names = "default";
2220 pinctrl-0 = <&rx_swr_active>;
2221 #sound-dai-cells = <1>;
2225 compatible = "qcom,soundwire-v2.0.0";
2229 clock-names = "iface";
2232 qcom,din-ports = <0>;
2233 qcom,dout-ports = <10>;
2235 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2236 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2237 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2238 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2239 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2240 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2241 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2242 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2243 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2245 #address-cells = <2>;
2246 #size-cells = <0>;
2247 #sound-dai-cells = <1>;
2252 compatible = "qcom,sm8550-lpass-tx-macro";
2258 clock-names = "mclk", "macro", "dcodec", "fsgen";
2259 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2261 assigned-clock-rates = <19200000>;
2263 #clock-cells = <0>;
2264 clock-output-names = "mclk";
2265 pinctrl-names = "default";
2266 pinctrl-0 = <&tx_swr_active>;
2267 #sound-dai-cells = <1>;
2271 compatible = "qcom,sm8550-lpass-wsa-macro";
2277 clock-names = "mclk", "macro", "dcodec", "fsgen";
2279 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2280 assigned-clock-rates = <19200000>;
2282 #clock-cells = <0>;
2283 clock-output-names = "mclk";
2284 pinctrl-names = "default";
2285 pinctrl-0 = <&wsa_swr_active>;
2286 #sound-dai-cells = <1>;
2290 compatible = "qcom,soundwire-v2.0.0";
2294 clock-names = "iface";
2297 qcom,din-ports = <4>;
2298 qcom,dout-ports = <9>;
2300 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2301 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2302 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2303 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2304 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2305 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2306 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2307 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2308 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2310 #address-cells = <2>;
2311 #size-cells = <0>;
2312 #sound-dai-cells = <1>;
2317 compatible = "qcom,soundwire-v2.0.0";
2321 interrupt-names = "core", "wakeup";
2323 clock-names = "iface";
2326 qcom,din-ports = <4>;
2327 qcom,dout-ports = <0>;
2328 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2329 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2330 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2331 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2332 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2333 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2334 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2335 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2336 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2338 #address-cells = <2>;
2339 #size-cells = <0>;
2340 #sound-dai-cells = <1>;
2345 compatible = "qcom,sm8550-lpass-va-macro";
2350 clock-names = "mclk", "macro", "dcodec";
2352 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2353 assigned-clock-rates = <19200000>;
2355 #clock-cells = <0>;
2356 clock-output-names = "fsgen";
2357 #sound-dai-cells = <1>;
2361 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2364 gpio-controller;
2365 #gpio-cells = <2>;
2366 gpio-ranges = <&lpass_tlmm 0 0 23>;
2370 clock-names = "core", "audio";
2372 tx_swr_active: tx-swr-active-state {
2373 clk-pins {
2376 drive-strength = <2>;
2377 slew-rate = <1>;
2378 bias-disable;
2381 data-pins {
2384 drive-strength = <2>;
2385 slew-rate = <1>;
2386 bias-bus-hold;
2390 rx_swr_active: rx-swr-active-state {
2391 clk-pins {
2394 drive-strength = <2>;
2395 slew-rate = <1>;
2396 bias-disable;
2399 data-pins {
2402 drive-strength = <2>;
2403 slew-rate = <1>;
2404 bias-bus-hold;
2408 dmic01_default: dmic01-default-state {
2409 clk-pins {
2412 drive-strength = <8>;
2413 output-high;
2416 data-pins {
2419 drive-strength = <8>;
2420 input-enable;
2424 dmic02_default: dmic02-default-state {
2425 clk-pins {
2428 drive-strength = <8>;
2429 output-high;
2432 data-pins {
2435 drive-strength = <8>;
2436 input-enable;
2440 wsa_swr_active: wsa-swr-active-state {
2441 clk-pins {
2444 drive-strength = <2>;
2445 slew-rate = <1>;
2446 bias-disable;
2449 data-pins {
2452 drive-strength = <2>;
2453 slew-rate = <1>;
2454 bias-bus-hold;
2458 wsa2_swr_active: wsa2-swr-active-state {
2459 clk-pins {
2462 drive-strength = <2>;
2463 slew-rate = <1>;
2464 bias-disable;
2467 data-pins {
2470 drive-strength = <2>;
2471 slew-rate = <1>;
2472 bias-bus-hold;
2478 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2480 #interconnect-cells = <2>;
2481 qcom,bcm-voters = <&apps_bcm_voter>;
2485 compatible = "qcom,sm8550-lpass-lpicx-noc";
2487 #interconnect-cells = <2>;
2488 qcom,bcm-voters = <&apps_bcm_voter>;
2492 compatible = "qcom,sm8550-lpass-ag-noc";
2494 #interconnect-cells = <2>;
2495 qcom,bcm-voters = <&apps_bcm_voter>;
2499 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2504 interrupt-names = "hc_irq", "pwr_irq";
2509 clock-names = "iface", "core", "xo";
2511 qcom,dll-config = <0x0007642c>;
2512 qcom,ddr-config = <0x80040868>;
2513 power-domains = <&rpmhpd RPMHPD_CX>;
2514 operating-points-v2 = <&sdhc2_opp_table>;
2518 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2519 bus-width = <4>;
2520 dma-coherent;
2522 /* Forbid SDR104/SDR50 - broken hw! */
2523 sdhci-caps-mask = <0x3 0>;
2527 sdhc2_opp_table: opp-table {
2528 compatible = "operating-points-v2";
2530 opp-19200000 {
2531 opp-hz = /bits/ 64 <19200000>;
2532 required-opps = <&rpmhpd_opp_min_svs>;
2535 opp-50000000 {
2536 opp-hz = /bits/ 64 <50000000>;
2537 required-opps = <&rpmhpd_opp_low_svs>;
2540 opp-100000000 {
2541 opp-hz = /bits/ 64 <100000000>;
2542 required-opps = <&rpmhpd_opp_svs>;
2545 opp-202000000 {
2546 opp-hz = /bits/ 64 <202000000>;
2547 required-opps = <&rpmhpd_opp_svs_l1>;
2552 videocc: clock-controller@aaf0000 {
2553 compatible = "qcom,sm8550-videocc";
2557 power-domains = <&rpmhpd RPMHPD_MMCX>;
2558 required-opps = <&rpmhpd_opp_low_svs>;
2559 #clock-cells = <1>;
2560 #reset-cells = <1>;
2561 #power-domain-cells = <1>;
2564 mdss: display-subsystem@ae00000 {
2565 compatible = "qcom,sm8550-mdss";
2567 reg-names = "mdss";
2570 interrupt-controller;
2571 #interrupt-cells = <1>;
2580 power-domains = <&dispcc MDSS_GDSC>;
2583 interconnect-names = "mdp0-mem";
2587 #address-cells = <2>;
2588 #size-cells = <2>;
2593 mdss_mdp: display-controller@ae01000 {
2594 compatible = "qcom,sm8550-dpu";
2597 reg-names = "mdp", "vbif";
2599 interrupt-parent = <&mdss>;
2608 clock-names = "bus",
2615 power-domains = <&rpmhpd RPMHPD_MMCX>;
2617 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2618 assigned-clock-rates = <19200000>;
2620 operating-points-v2 = <&mdp_opp_table>;
2623 #address-cells = <1>;
2624 #size-cells = <0>;
2629 remote-endpoint = <&mdss_dsi0_in>;
2636 remote-endpoint = <&mdss_dsi1_in>;
2643 remote-endpoint = <&mdss_dp0_in>;
2648 mdp_opp_table: opp-table {
2649 compatible = "operating-points-v2";
2651 opp-200000000 {
2652 opp-hz = /bits/ 64 <200000000>;
2653 required-opps = <&rpmhpd_opp_low_svs>;
2656 opp-325000000 {
2657 opp-hz = /bits/ 64 <325000000>;
2658 required-opps = <&rpmhpd_opp_svs>;
2661 opp-375000000 {
2662 opp-hz = /bits/ 64 <375000000>;
2663 required-opps = <&rpmhpd_opp_svs_l1>;
2666 opp-514000000 {
2667 opp-hz = /bits/ 64 <514000000>;
2668 required-opps = <&rpmhpd_opp_nom>;
2673 mdss_dp0: displayport-controller@ae90000 {
2674 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2680 interrupt-parent = <&mdss>;
2687 clock-names = "core_iface",
2693 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2695 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2699 phy-names = "dp";
2701 #sound-dai-cells = <0>;
2703 operating-points-v2 = <&dp_opp_table>;
2704 power-domains = <&rpmhpd RPMHPD_MMCX>;
2709 #address-cells = <1>;
2710 #size-cells = <0>;
2715 remote-endpoint = <&dpu_intf0_out>;
2726 dp_opp_table: opp-table {
2727 compatible = "operating-points-v2";
2729 opp-162000000 {
2730 opp-hz = /bits/ 64 <162000000>;
2731 required-opps = <&rpmhpd_opp_low_svs_d1>;
2734 opp-270000000 {
2735 opp-hz = /bits/ 64 <270000000>;
2736 required-opps = <&rpmhpd_opp_low_svs>;
2739 opp-540000000 {
2740 opp-hz = /bits/ 64 <540000000>;
2741 required-opps = <&rpmhpd_opp_svs_l1>;
2744 opp-810000000 {
2745 opp-hz = /bits/ 64 <810000000>;
2746 required-opps = <&rpmhpd_opp_nom>;
2752 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2754 reg-names = "dsi_ctrl";
2756 interrupt-parent = <&mdss>;
2765 clock-names = "byte",
2772 power-domains = <&rpmhpd RPMHPD_MMCX>;
2774 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2776 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2779 operating-points-v2 = <&mdss_dsi_opp_table>;
2782 phy-names = "dsi";
2784 #address-cells = <1>;
2785 #size-cells = <0>;
2790 #address-cells = <1>;
2791 #size-cells = <0>;
2796 remote-endpoint = <&dpu_intf1_out>;
2807 mdss_dsi_opp_table: opp-table {
2808 compatible = "operating-points-v2";
2810 opp-187500000 {
2811 opp-hz = /bits/ 64 <187500000>;
2812 required-opps = <&rpmhpd_opp_low_svs>;
2815 opp-300000000 {
2816 opp-hz = /bits/ 64 <300000000>;
2817 required-opps = <&rpmhpd_opp_svs>;
2820 opp-358000000 {
2821 opp-hz = /bits/ 64 <358000000>;
2822 required-opps = <&rpmhpd_opp_svs_l1>;
2828 compatible = "qcom,sm8550-dsi-phy-4nm";
2832 reg-names = "dsi_phy",
2838 clock-names = "iface", "ref";
2840 #clock-cells = <1>;
2841 #phy-cells = <0>;
2847 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2849 reg-names = "dsi_ctrl";
2851 interrupt-parent = <&mdss>;
2860 clock-names = "byte",
2867 power-domains = <&rpmhpd RPMHPD_MMCX>;
2869 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2871 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2874 operating-points-v2 = <&mdss_dsi_opp_table>;
2877 phy-names = "dsi";
2879 #address-cells = <1>;
2880 #size-cells = <0>;
2885 #address-cells = <1>;
2886 #size-cells = <0>;
2891 remote-endpoint = <&dpu_intf2_out>;
2904 compatible = "qcom,sm8550-dsi-phy-4nm";
2908 reg-names = "dsi_phy",
2914 clock-names = "iface", "ref";
2916 #clock-cells = <1>;
2917 #phy-cells = <0>;
2923 dispcc: clock-controller@af00000 {
2924 compatible = "qcom,sm8550-dispcc";
2942 power-domains = <&rpmhpd RPMHPD_MMCX>;
2943 required-opps = <&rpmhpd_opp_low_svs>;
2944 #clock-cells = <1>;
2945 #reset-cells = <1>;
2946 #power-domain-cells = <1>;
2950 compatible = "qcom,sm8550-snps-eusb2-phy";
2952 #phy-cells = <0>;
2955 clock-names = "ref";
2963 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2970 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2972 power-domains = <&gcc USB3_PHY_GDSC>;
2976 reset-names = "phy", "common";
2978 #clock-cells = <1>;
2979 #phy-cells = <1>;
2984 #address-cells = <1>;
2985 #size-cells = <0>;
3011 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3013 #address-cells = <2>;
3014 #size-cells = <2>;
3023 clock-names = "cfg_noc",
3030 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3032 assigned-clock-rates = <19200000>, <200000000>;
3034 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3038 interrupt-names = "hs_phy_irq",
3043 power-domains = <&gcc USB30_PRIM_GDSC>;
3044 required-opps = <&rpmhpd_opp_nom>;
3050 interconnect-names = "usb-ddr", "apps-usb";
3064 phy-names = "usb2-phy", "usb3-phy";
3067 #address-cells = <1>;
3068 #size-cells = <0>;
3087 pdc: interrupt-controller@b220000 {
3088 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3090 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3093 #interrupt-cells = <2>;
3094 interrupt-parent = <&intc>;
3095 interrupt-controller;
3098 tsens0: thermal-sensor@c271000 {
3099 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3105 interrupt-names = "uplow", "critical";
3106 #thermal-sensor-cells = <1>;
3109 tsens1: thermal-sensor@c272000 {
3110 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3116 interrupt-names = "uplow", "critical";
3117 #thermal-sensor-cells = <1>;
3120 tsens2: thermal-sensor@c273000 {
3121 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3127 interrupt-names = "uplow", "critical";
3128 #thermal-sensor-cells = <1>;
3131 aoss_qmp: power-management@c300000 {
3132 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3134 interrupt-parent = <&ipcc>;
3135 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3139 #clock-cells = <0>;
3143 compatible = "qcom,rpmh-stats";
3148 compatible = "qcom,spmi-pmic-arb";
3154 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3155 interrupt-names = "periph_irq";
3156 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3159 qcom,bus-id = <0>;
3160 #address-cells = <2>;
3161 #size-cells = <0>;
3162 interrupt-controller;
3163 #interrupt-cells = <4>;
3167 compatible = "qcom,sm8550-tlmm";
3170 gpio-controller;
3171 #gpio-cells = <2>;
3172 interrupt-controller;
3173 #interrupt-cells = <2>;
3174 gpio-ranges = <&tlmm 0 0 211>;
3175 wakeup-parent = <&pdc>;
3177 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3181 drive-strength = <2>;
3182 bias-pull-up;
3185 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3189 drive-strength = <2>;
3190 bias-pull-up;
3193 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3197 drive-strength = <2>;
3198 bias-pull-up;
3201 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3205 drive-strength = <2>;
3206 bias-pull-up;
3209 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3213 drive-strength = <2>;
3214 bias-pull-up;
3217 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3221 drive-strength = <2>;
3222 bias-pull-up;
3225 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3229 drive-strength = <2>;
3230 bias-pull-up;
3233 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3237 drive-strength = <2>;
3238 bias-pull-up;
3241 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3245 drive-strength = <2>;
3246 bias-pull-up;
3249 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3253 drive-strength = <2>;
3254 bias-pull-up;
3257 pcie0_default_state: pcie0-default-state {
3258 perst-pins {
3261 drive-strength = <2>;
3262 bias-pull-down;
3265 clkreq-pins {
3268 drive-strength = <2>;
3269 bias-pull-up;
3272 wake-pins {
3275 drive-strength = <2>;
3276 bias-pull-up;
3280 pcie1_default_state: pcie1-default-state {
3281 perst-pins {
3284 drive-strength = <2>;
3285 bias-pull-down;
3288 clkreq-pins {
3291 drive-strength = <2>;
3292 bias-pull-up;
3295 wake-pins {
3298 drive-strength = <2>;
3299 bias-pull-up;
3303 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3307 drive-strength = <2>;
3308 bias-pull-up = <2200>;
3311 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3315 drive-strength = <2>;
3316 bias-pull-up = <2200>;
3319 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3323 drive-strength = <2>;
3324 bias-pull-up = <2200>;
3327 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3331 drive-strength = <2>;
3332 bias-pull-up = <2200>;
3335 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3339 drive-strength = <2>;
3340 bias-pull-up = <2200>;
3343 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3347 drive-strength = <2>;
3348 bias-pull-up = <2200>;
3351 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3355 drive-strength = <2>;
3356 bias-pull-up = <2200>;
3359 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3360 scl-pins {
3363 drive-strength = <2>;
3364 bias-pull-up = <2200>;
3367 sda-pins {
3370 drive-strength = <2>;
3371 bias-pull-up = <2200>;
3375 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3379 drive-strength = <2>;
3380 bias-pull-up = <2200>;
3383 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3387 drive-strength = <2>;
3388 bias-pull-up = <2200>;
3391 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3395 drive-strength = <2>;
3396 bias-pull-up = <2200>;
3399 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3403 drive-strength = <2>;
3404 bias-pull-up = <2200>;
3407 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3411 drive-strength = <2>;
3412 bias-pull-up = <2200>;
3415 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3419 drive-strength = <2>;
3420 bias-pull-up = <2200>;
3423 qup_spi0_cs: qup-spi0-cs-state {
3426 drive-strength = <6>;
3427 bias-disable;
3430 qup_spi0_data_clk: qup-spi0-data-clk-state {
3434 drive-strength = <6>;
3435 bias-disable;
3438 qup_spi1_cs: qup-spi1-cs-state {
3441 drive-strength = <6>;
3442 bias-disable;
3445 qup_spi1_data_clk: qup-spi1-data-clk-state {
3449 drive-strength = <6>;
3450 bias-disable;
3453 qup_spi2_cs: qup-spi2-cs-state {
3456 drive-strength = <6>;
3457 bias-disable;
3460 qup_spi2_data_clk: qup-spi2-data-clk-state {
3464 drive-strength = <6>;
3465 bias-disable;
3468 qup_spi3_cs: qup-spi3-cs-state {
3471 drive-strength = <6>;
3472 bias-disable;
3475 qup_spi3_data_clk: qup-spi3-data-clk-state {
3479 drive-strength = <6>;
3480 bias-disable;
3483 qup_spi4_cs: qup-spi4-cs-state {
3486 drive-strength = <6>;
3487 bias-disable;
3490 qup_spi4_data_clk: qup-spi4-data-clk-state {
3494 drive-strength = <6>;
3495 bias-disable;
3498 qup_spi5_cs: qup-spi5-cs-state {
3501 drive-strength = <6>;
3502 bias-disable;
3505 qup_spi5_data_clk: qup-spi5-data-clk-state {
3509 drive-strength = <6>;
3510 bias-disable;
3513 qup_spi6_cs: qup-spi6-cs-state {
3516 drive-strength = <6>;
3517 bias-disable;
3520 qup_spi6_data_clk: qup-spi6-data-clk-state {
3524 drive-strength = <6>;
3525 bias-disable;
3528 qup_spi8_cs: qup-spi8-cs-state {
3531 drive-strength = <6>;
3532 bias-disable;
3535 qup_spi8_data_clk: qup-spi8-data-clk-state {
3539 drive-strength = <6>;
3540 bias-disable;
3543 qup_spi9_cs: qup-spi9-cs-state {
3546 drive-strength = <6>;
3547 bias-disable;
3550 qup_spi9_data_clk: qup-spi9-data-clk-state {
3554 drive-strength = <6>;
3555 bias-disable;
3558 qup_spi10_cs: qup-spi10-cs-state {
3561 drive-strength = <6>;
3562 bias-disable;
3565 qup_spi10_data_clk: qup-spi10-data-clk-state {
3569 drive-strength = <6>;
3570 bias-disable;
3573 qup_spi11_cs: qup-spi11-cs-state {
3576 drive-strength = <6>;
3577 bias-disable;
3580 qup_spi11_data_clk: qup-spi11-data-clk-state {
3584 drive-strength = <6>;
3585 bias-disable;
3588 qup_spi12_cs: qup-spi12-cs-state {
3591 drive-strength = <6>;
3592 bias-disable;
3595 qup_spi12_data_clk: qup-spi12-data-clk-state {
3599 drive-strength = <6>;
3600 bias-disable;
3603 qup_spi13_cs: qup-spi13-cs-state {
3606 drive-strength = <6>;
3607 bias-disable;
3610 qup_spi13_data_clk: qup-spi13-data-clk-state {
3614 drive-strength = <6>;
3615 bias-disable;
3618 qup_spi15_cs: qup-spi15-cs-state {
3621 drive-strength = <6>;
3622 bias-disable;
3625 qup_spi15_data_clk: qup-spi15-data-clk-state {
3629 drive-strength = <6>;
3630 bias-disable;
3633 qup_uart7_default: qup-uart7-default-state {
3637 drive-strength = <2>;
3638 bias-disable;
3641 sdc2_sleep: sdc2-sleep-state {
3642 clk-pins {
3644 bias-disable;
3645 drive-strength = <2>;
3648 cmd-pins {
3650 bias-pull-up;
3651 drive-strength = <2>;
3654 data-pins {
3656 bias-pull-up;
3657 drive-strength = <2>;
3661 sdc2_default: sdc2-default-state {
3662 clk-pins {
3664 bias-disable;
3665 drive-strength = <16>;
3668 cmd-pins {
3670 bias-pull-up;
3671 drive-strength = <10>;
3674 data-pins {
3676 bias-pull-up;
3677 drive-strength = <10>;
3683 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3685 #iommu-cells = <2>;
3686 #global-interrupts = <1>;
3786 intc: interrupt-controller@17100000 {
3787 compatible = "arm,gic-v3";
3791 #interrupt-cells = <3>;
3792 interrupt-controller;
3793 #redistributor-regions = <1>;
3794 redistributor-stride = <0 0x40000>;
3796 #address-cells = <2>;
3797 #size-cells = <2>;
3799 gic_its: msi-controller@17140000 {
3800 compatible = "arm,gic-v3-its";
3802 msi-controller;
3803 #msi-cells = <1>;
3808 compatible = "arm,armv7-timer-mem";
3811 #address-cells = <1>;
3812 #size-cells = <1>;
3817 frame-number = <0>;
3824 frame-number = <1>;
3831 frame-number = <2>;
3838 frame-number = <3>;
3845 frame-number = <4>;
3852 frame-number = <5>;
3859 frame-number = <6>;
3867 compatible = "qcom,rpmh-rsc";
3872 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3876 qcom,tcs-offset = <0xd00>;
3877 qcom,drv-id = <2>;
3878 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3880 power-domains = <&CLUSTER_PD>;
3882 apps_bcm_voter: bcm-voter {
3883 compatible = "qcom,bcm-voter";
3886 rpmhcc: clock-controller {
3887 compatible = "qcom,sm8550-rpmh-clk";
3888 #clock-cells = <1>;
3889 clock-names = "xo";
3893 rpmhpd: power-controller { label
3894 compatible = "qcom,sm8550-rpmhpd";
3895 #power-domain-cells = <1>;
3896 operating-points-v2 = <&rpmhpd_opp_table>;
3898 rpmhpd_opp_table: opp-table {
3899 compatible = "operating-points-v2";
3901 rpmhpd_opp_ret: opp-16 {
3902 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3905 rpmhpd_opp_min_svs: opp-48 {
3906 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3909 rpmhpd_opp_low_svs_d2: opp-52 {
3910 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3913 rpmhpd_opp_low_svs_d1: opp-56 {
3914 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3917 rpmhpd_opp_low_svs_d0: opp-60 {
3918 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3921 rpmhpd_opp_low_svs: opp-64 {
3922 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3925 rpmhpd_opp_low_svs_l1: opp-80 {
3926 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3929 rpmhpd_opp_svs: opp-128 {
3930 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3933 rpmhpd_opp_svs_l0: opp-144 {
3934 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3937 rpmhpd_opp_svs_l1: opp-192 {
3938 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3941 rpmhpd_opp_nom: opp-256 {
3942 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3945 rpmhpd_opp_nom_l1: opp-320 {
3946 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3949 rpmhpd_opp_nom_l2: opp-336 {
3950 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3953 rpmhpd_opp_turbo: opp-384 {
3954 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3957 rpmhpd_opp_turbo_l1: opp-416 {
3958 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3965 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3969 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3971 clock-names = "xo", "alternate";
3975 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3976 #freq-domain-cells = <1>;
3977 #clock-cells = <1>;
3981 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3986 operating-points-v2 = <&llcc_bwmon_opp_table>;
3988 llcc_bwmon_opp_table: opp-table {
3989 compatible = "operating-points-v2";
3991 opp-0 {
3992 opp-peak-kBps = <2086000>;
3995 opp-1 {
3996 opp-peak-kBps = <2929000>;
3999 opp-2 {
4000 opp-peak-kBps = <5931000>;
4003 opp-3 {
4004 opp-peak-kBps = <6515000>;
4007 opp-4 {
4008 opp-peak-kBps = <7980000>;
4011 opp-5 {
4012 opp-peak-kBps = <10437000>;
4015 opp-6 {
4016 opp-peak-kBps = <12157000>;
4019 opp-7 {
4020 opp-peak-kBps = <14060000>;
4023 opp-8 {
4024 opp-peak-kBps = <16113000>;
4030 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4035 operating-points-v2 = <&cpu_bwmon_opp_table>;
4037 cpu_bwmon_opp_table: opp-table {
4038 compatible = "operating-points-v2";
4040 opp-0 {
4041 opp-peak-kBps = <4577000>;
4044 opp-1 {
4045 opp-peak-kBps = <7110000>;
4048 opp-2 {
4049 opp-peak-kBps = <9155000>;
4052 opp-3 {
4053 opp-peak-kBps = <12298000>;
4056 opp-4 {
4057 opp-peak-kBps = <14236000>;
4060 opp-5 {
4061 opp-peak-kBps = <16265000>;
4067 compatible = "qcom,sm8550-gem-noc";
4069 #interconnect-cells = <2>;
4070 qcom,bcm-voters = <&apps_bcm_voter>;
4073 system-cache-controller@25000000 {
4074 compatible = "qcom,sm8550-llcc";
4080 reg-names = "llcc0_base",
4089 compatible = "qcom,sm8550-nsp-noc";
4091 #interconnect-cells = <2>;
4092 qcom,bcm-voters = <&apps_bcm_voter>;
4096 compatible = "qcom,sm8550-cdsp-pas";
4099 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4104 interrupt-names = "wdog", "fatal", "ready",
4105 "handover", "stop-ack";
4108 clock-names = "xo";
4110 power-domains = <&rpmhpd RPMHPD_CX>,
4111 <&rpmhpd RPMHPD_MXC>,
4112 <&rpmhpd RPMHPD_NSP>;
4113 power-domain-names = "cx", "mxc", "nsp";
4117 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4121 qcom,smem-states = <&smp2p_cdsp_out 0>;
4122 qcom,smem-state-names = "stop";
4126 glink-edge {
4127 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4134 qcom,remote-pid = <5>;
4138 qcom,glink-channels = "fastrpcglink-apps-dsp";
4140 qcom,non-secure-domain;
4141 #address-cells = <1>;
4142 #size-cells = <0>;
4144 compute-cb@1 {
4145 compatible = "qcom,fastrpc-compute-cb";
4150 dma-coherent;
4153 compute-cb@2 {
4154 compatible = "qcom,fastrpc-compute-cb";
4159 dma-coherent;
4162 compute-cb@3 {
4163 compatible = "qcom,fastrpc-compute-cb";
4168 dma-coherent;
4171 compute-cb@4 {
4172 compatible = "qcom,fastrpc-compute-cb";
4177 dma-coherent;
4180 compute-cb@5 {
4181 compatible = "qcom,fastrpc-compute-cb";
4186 dma-coherent;
4189 compute-cb@6 {
4190 compatible = "qcom,fastrpc-compute-cb";
4195 dma-coherent;
4198 compute-cb@7 {
4199 compatible = "qcom,fastrpc-compute-cb";
4204 dma-coherent;
4207 compute-cb@8 {
4208 compatible = "qcom,fastrpc-compute-cb";
4213 dma-coherent;
4222 thermal-zones {
4223 aoss0-thermal {
4224 polling-delay-passive = <0>;
4225 polling-delay = <0>;
4226 thermal-sensors = <&tsens0 0>;
4229 thermal-engine-config {
4235 reset-mon-config {
4243 cpuss0-thermal {
4244 polling-delay-passive = <0>;
4245 polling-delay = <0>;
4246 thermal-sensors = <&tsens0 1>;
4249 thermal-engine-config {
4255 reset-mon-config {
4263 cpuss1-thermal {
4264 polling-delay-passive = <0>;
4265 polling-delay = <0>;
4266 thermal-sensors = <&tsens0 2>;
4269 thermal-engine-config {
4275 reset-mon-config {
4283 cpuss2-thermal {
4284 polling-delay-passive = <0>;
4285 polling-delay = <0>;
4286 thermal-sensors = <&tsens0 3>;
4289 thermal-engine-config {
4295 reset-mon-config {
4303 cpuss3-thermal {
4304 polling-delay-passive = <0>;
4305 polling-delay = <0>;
4306 thermal-sensors = <&tsens0 4>;
4309 thermal-engine-config {
4315 reset-mon-config {
4323 cpu3-top-thermal {
4324 polling-delay-passive = <0>;
4325 polling-delay = <0>;
4326 thermal-sensors = <&tsens0 5>;
4329 cpu3_top_alert0: trip-point0 {
4335 cpu3_top_alert1: trip-point1 {
4341 cpu3_top_crit: cpu-critical {
4349 cpu3-bottom-thermal {
4350 polling-delay-passive = <0>;
4351 polling-delay = <0>;
4352 thermal-sensors = <&tsens0 6>;
4355 cpu3_bottom_alert0: trip-point0 {
4361 cpu3_bottom_alert1: trip-point1 {
4367 cpu3_bottom_crit: cpu-critical {
4375 cpu4-top-thermal {
4376 polling-delay-passive = <0>;
4377 polling-delay = <0>;
4378 thermal-sensors = <&tsens0 7>;
4381 cpu4_top_alert0: trip-point0 {
4387 cpu4_top_alert1: trip-point1 {
4393 cpu4_top_crit: cpu-critical {
4401 cpu4-bottom-thermal {
4402 polling-delay-passive = <0>;
4403 polling-delay = <0>;
4404 thermal-sensors = <&tsens0 8>;
4407 cpu4_bottom_alert0: trip-point0 {
4413 cpu4_bottom_alert1: trip-point1 {
4419 cpu4_bottom_crit: cpu-critical {
4427 cpu5-top-thermal {
4428 polling-delay-passive = <0>;
4429 polling-delay = <0>;
4430 thermal-sensors = <&tsens0 9>;
4433 cpu5_top_alert0: trip-point0 {
4439 cpu5_top_alert1: trip-point1 {
4445 cpu5_top_crit: cpu-critical {
4453 cpu5-bottom-thermal {
4454 polling-delay-passive = <0>;
4455 polling-delay = <0>;
4456 thermal-sensors = <&tsens0 10>;
4459 cpu5_bottom_alert0: trip-point0 {
4465 cpu5_bottom_alert1: trip-point1 {
4471 cpu5_bottom_crit: cpu-critical {
4479 cpu6-top-thermal {
4480 polling-delay-passive = <0>;
4481 polling-delay = <0>;
4482 thermal-sensors = <&tsens0 11>;
4485 cpu6_top_alert0: trip-point0 {
4491 cpu6_top_alert1: trip-point1 {
4497 cpu6_top_crit: cpu-critical {
4505 cpu6-bottom-thermal {
4506 polling-delay-passive = <0>;
4507 polling-delay = <0>;
4508 thermal-sensors = <&tsens0 12>;
4511 cpu6_bottom_alert0: trip-point0 {
4517 cpu6_bottom_alert1: trip-point1 {
4523 cpu6_bottom_crit: cpu-critical {
4531 cpu7-top-thermal {
4532 polling-delay-passive = <0>;
4533 polling-delay = <0>;
4534 thermal-sensors = <&tsens0 13>;
4537 cpu7_top_alert0: trip-point0 {
4543 cpu7_top_alert1: trip-point1 {
4549 cpu7_top_crit: cpu-critical {
4557 cpu7-middle-thermal {
4558 polling-delay-passive = <0>;
4559 polling-delay = <0>;
4560 thermal-sensors = <&tsens0 14>;
4563 cpu7_middle_alert0: trip-point0 {
4569 cpu7_middle_alert1: trip-point1 {
4575 cpu7_middle_crit: cpu-critical {
4583 cpu7-bottom-thermal {
4584 polling-delay-passive = <0>;
4585 polling-delay = <0>;
4586 thermal-sensors = <&tsens0 15>;
4589 cpu7_bottom_alert0: trip-point0 {
4595 cpu7_bottom_alert1: trip-point1 {
4601 cpu7_bottom_crit: cpu-critical {
4609 aoss1-thermal {
4610 polling-delay-passive = <0>;
4611 polling-delay = <0>;
4612 thermal-sensors = <&tsens1 0>;
4615 thermal-engine-config {
4621 reset-mon-config {
4629 cpu0-thermal {
4630 polling-delay-passive = <0>;
4631 polling-delay = <0>;
4632 thermal-sensors = <&tsens1 1>;
4635 cpu0_alert0: trip-point0 {
4641 cpu0_alert1: trip-point1 {
4647 cpu0_crit: cpu-critical {
4655 cpu1-thermal {
4656 polling-delay-passive = <0>;
4657 polling-delay = <0>;
4658 thermal-sensors = <&tsens1 2>;
4661 cpu1_alert0: trip-point0 {
4667 cpu1_alert1: trip-point1 {
4673 cpu1_crit: cpu-critical {
4681 cpu2-thermal {
4682 polling-delay-passive = <0>;
4683 polling-delay = <0>;
4684 thermal-sensors = <&tsens1 3>;
4687 cpu2_alert0: trip-point0 {
4693 cpu2_alert1: trip-point1 {
4699 cpu2_crit: cpu-critical {
4707 cdsp0-thermal {
4708 polling-delay-passive = <10>;
4709 polling-delay = <0>;
4710 thermal-sensors = <&tsens2 4>;
4713 thermal-engine-config {
4719 thermal-hal-config {
4725 reset-mon-config {
4731 cdsp0_junction_config: junction-config {
4739 cdsp1-thermal {
4740 polling-delay-passive = <10>;
4741 polling-delay = <0>;
4742 thermal-sensors = <&tsens2 5>;
4745 thermal-engine-config {
4751 thermal-hal-config {
4757 reset-mon-config {
4763 cdsp1_junction_config: junction-config {
4771 cdsp2-thermal {
4772 polling-delay-passive = <10>;
4773 polling-delay = <0>;
4774 thermal-sensors = <&tsens2 6>;
4777 thermal-engine-config {
4783 thermal-hal-config {
4789 reset-mon-config {
4795 cdsp2_junction_config: junction-config {
4803 cdsp3-thermal {
4804 polling-delay-passive = <10>;
4805 polling-delay = <0>;
4806 thermal-sensors = <&tsens2 7>;
4809 thermal-engine-config {
4815 thermal-hal-config {
4821 reset-mon-config {
4827 cdsp3_junction_config: junction-config {
4835 video-thermal {
4836 polling-delay-passive = <0>;
4837 polling-delay = <0>;
4838 thermal-sensors = <&tsens1 8>;
4841 thermal-engine-config {
4847 reset-mon-config {
4855 mem-thermal {
4856 polling-delay-passive = <10>;
4857 polling-delay = <0>;
4858 thermal-sensors = <&tsens1 9>;
4861 thermal-engine-config {
4867 ddr_config0: ddr0-config {
4873 reset-mon-config {
4881 modem0-thermal {
4882 polling-delay-passive = <0>;
4883 polling-delay = <0>;
4884 thermal-sensors = <&tsens1 10>;
4887 thermal-engine-config {
4893 mdmss0_config0: mdmss0-config0 {
4899 mdmss0_config1: mdmss0-config1 {
4905 reset-mon-config {
4913 modem1-thermal {
4914 polling-delay-passive = <0>;
4915 polling-delay = <0>;
4916 thermal-sensors = <&tsens1 11>;
4919 thermal-engine-config {
4925 mdmss1_config0: mdmss1-config0 {
4931 mdmss1_config1: mdmss1-config1 {
4937 reset-mon-config {
4945 modem2-thermal {
4946 polling-delay-passive = <0>;
4947 polling-delay = <0>;
4948 thermal-sensors = <&tsens1 12>;
4951 thermal-engine-config {
4957 mdmss2_config0: mdmss2-config0 {
4963 mdmss2_config1: mdmss2-config1 {
4969 reset-mon-config {
4977 modem3-thermal {
4978 polling-delay-passive = <0>;
4979 polling-delay = <0>;
4980 thermal-sensors = <&tsens1 13>;
4983 thermal-engine-config {
4989 mdmss3_config0: mdmss3-config0 {
4995 mdmss3_config1: mdmss3-config1 {
5001 reset-mon-config {
5009 camera0-thermal {
5010 polling-delay-passive = <0>;
5011 polling-delay = <0>;
5012 thermal-sensors = <&tsens1 14>;
5015 thermal-engine-config {
5021 reset-mon-config {
5029 camera1-thermal {
5030 polling-delay-passive = <0>;
5031 polling-delay = <0>;
5032 thermal-sensors = <&tsens1 15>;
5035 thermal-engine-config {
5041 reset-mon-config {
5049 aoss2-thermal {
5050 polling-delay-passive = <0>;
5051 polling-delay = <0>;
5052 thermal-sensors = <&tsens2 0>;
5055 thermal-engine-config {
5061 reset-mon-config {
5069 gpuss-0-thermal {
5070 polling-delay-passive = <10>;
5071 polling-delay = <0>;
5072 thermal-sensors = <&tsens2 1>;
5075 thermal-engine-config {
5081 thermal-hal-config {
5087 reset-mon-config {
5093 gpu0_junction_config: junction-config {
5101 gpuss-1-thermal {
5102 polling-delay-passive = <10>;
5103 polling-delay = <0>;
5104 thermal-sensors = <&tsens2 2>;
5107 thermal-engine-config {
5113 thermal-hal-config {
5119 reset-mon-config {
5125 gpu1_junction_config: junction-config {
5133 gpuss-2-thermal {
5134 polling-delay-passive = <10>;
5135 polling-delay = <0>;
5136 thermal-sensors = <&tsens2 3>;
5139 thermal-engine-config {
5145 thermal-hal-config {
5151 reset-mon-config {
5157 gpu2_junction_config: junction-config {
5165 gpuss-3-thermal {
5166 polling-delay-passive = <10>;
5167 polling-delay = <0>;
5168 thermal-sensors = <&tsens2 4>;
5171 thermal-engine-config {
5177 thermal-hal-config {
5183 reset-mon-config {
5189 gpu3_junction_config: junction-config {
5197 gpuss-4-thermal {
5198 polling-delay-passive = <10>;
5199 polling-delay = <0>;
5200 thermal-sensors = <&tsens2 5>;
5203 thermal-engine-config {
5209 thermal-hal-config {
5215 reset-mon-config {
5221 gpu4_junction_config: junction-config {
5229 gpuss-5-thermal {
5230 polling-delay-passive = <10>;
5231 polling-delay = <0>;
5232 thermal-sensors = <&tsens2 6>;
5235 thermal-engine-config {
5241 thermal-hal-config {
5247 reset-mon-config {
5253 gpu5_junction_config: junction-config {
5261 gpuss-6-thermal {
5262 polling-delay-passive = <10>;
5263 polling-delay = <0>;
5264 thermal-sensors = <&tsens2 7>;
5267 thermal-engine-config {
5273 thermal-hal-config {
5279 reset-mon-config {
5285 gpu6_junction_config: junction-config {
5293 gpuss-7-thermal {
5294 polling-delay-passive = <10>;
5295 polling-delay = <0>;
5296 thermal-sensors = <&tsens2 8>;
5299 thermal-engine-config {
5305 thermal-hal-config {
5311 reset-mon-config {
5317 gpu7_junction_config: junction-config {
5327 compatible = "arm,armv8-timer";