Lines Matching +full:ports +full:- +full:offset2
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
44 bi_tcxo_div2: bi-tcxo-div2-clk {
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
48 clock-mult = <1>;
49 clock-div = <2>;
52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
53 #clock-cells = <0>;
54 compatible = "fixed-factor-clock";
56 clock-mult = <1>;
57 clock-div = <2>;
60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
67 #address-cells = <2>;
68 #size-cells = <0>;
72 compatible = "arm,cortex-a510";
75 enable-method = "psci";
76 next-level-cache = <&L2_0>;
77 power-domains = <&CPU_PD0>;
78 power-domain-names = "psci";
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 capacity-dmips-mhz = <1024>;
81 dynamic-power-coefficient = <100>;
82 #cooling-cells = <2>;
83 L2_0: l2-cache {
85 cache-level = <2>;
86 cache-unified;
87 next-level-cache = <&L3_0>;
88 L3_0: l3-cache {
90 cache-level = <3>;
91 cache-unified;
98 compatible = "arm,cortex-a510";
101 enable-method = "psci";
102 next-level-cache = <&L2_100>;
103 power-domains = <&CPU_PD1>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 capacity-dmips-mhz = <1024>;
107 dynamic-power-coefficient = <100>;
108 #cooling-cells = <2>;
109 L2_100: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
119 compatible = "arm,cortex-a510";
122 enable-method = "psci";
123 next-level-cache = <&L2_200>;
124 power-domains = <&CPU_PD2>;
125 power-domain-names = "psci";
126 qcom,freq-domain = <&cpufreq_hw 0>;
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
129 #cooling-cells = <2>;
130 L2_200: l2-cache {
132 cache-level = <2>;
133 cache-unified;
134 next-level-cache = <&L3_0>;
140 compatible = "arm,cortex-a715";
143 enable-method = "psci";
144 next-level-cache = <&L2_300>;
145 power-domains = <&CPU_PD3>;
146 power-domain-names = "psci";
147 qcom,freq-domain = <&cpufreq_hw 1>;
148 capacity-dmips-mhz = <1792>;
149 dynamic-power-coefficient = <270>;
150 #cooling-cells = <2>;
151 L2_300: l2-cache {
153 cache-level = <2>;
154 cache-unified;
155 next-level-cache = <&L3_0>;
161 compatible = "arm,cortex-a715";
164 enable-method = "psci";
165 next-level-cache = <&L2_400>;
166 power-domains = <&CPU_PD4>;
167 power-domain-names = "psci";
168 qcom,freq-domain = <&cpufreq_hw 1>;
169 capacity-dmips-mhz = <1792>;
170 dynamic-power-coefficient = <270>;
171 #cooling-cells = <2>;
172 L2_400: l2-cache {
174 cache-level = <2>;
175 cache-unified;
176 next-level-cache = <&L3_0>;
182 compatible = "arm,cortex-a710";
185 enable-method = "psci";
186 next-level-cache = <&L2_500>;
187 power-domains = <&CPU_PD5>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 1>;
190 capacity-dmips-mhz = <1792>;
191 dynamic-power-coefficient = <270>;
192 #cooling-cells = <2>;
193 L2_500: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&L3_0>;
203 compatible = "arm,cortex-a710";
206 enable-method = "psci";
207 next-level-cache = <&L2_600>;
208 power-domains = <&CPU_PD6>;
209 power-domain-names = "psci";
210 qcom,freq-domain = <&cpufreq_hw 1>;
211 capacity-dmips-mhz = <1792>;
212 dynamic-power-coefficient = <270>;
213 #cooling-cells = <2>;
214 L2_600: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&L3_0>;
224 compatible = "arm,cortex-x3";
227 enable-method = "psci";
228 next-level-cache = <&L2_700>;
229 power-domains = <&CPU_PD7>;
230 power-domain-names = "psci";
231 qcom,freq-domain = <&cpufreq_hw 2>;
232 capacity-dmips-mhz = <1894>;
233 dynamic-power-coefficient = <588>;
234 #cooling-cells = <2>;
235 L2_700: l2-cache {
237 cache-level = <2>;
238 cache-unified;
239 next-level-cache = <&L3_0>;
243 cpu-map {
279 idle-states {
280 entry-method = "psci";
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "silver-rail-power-collapse";
285 arm,psci-suspend-param = <0x40000004>;
286 entry-latency-us = <550>;
287 exit-latency-us = <750>;
288 min-residency-us = <6700>;
289 local-timer-stop;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "gold-rail-power-collapse";
295 arm,psci-suspend-param = <0x40000004>;
296 entry-latency-us = <600>;
297 exit-latency-us = <1300>;
298 min-residency-us = <8136>;
299 local-timer-stop;
302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
303 compatible = "arm,idle-state";
304 idle-state-name = "goldplus-rail-power-collapse";
305 arm,psci-suspend-param = <0x40000004>;
306 entry-latency-us = <500>;
307 exit-latency-us = <1350>;
308 min-residency-us = <7480>;
309 local-timer-stop;
313 domain-idle-states {
314 CLUSTER_SLEEP_0: cluster-sleep-0 {
315 compatible = "domain-idle-state";
316 arm,psci-suspend-param = <0x41000044>;
317 entry-latency-us = <750>;
318 exit-latency-us = <2350>;
319 min-residency-us = <9144>;
322 CLUSTER_SLEEP_1: cluster-sleep-1 {
323 compatible = "domain-idle-state";
324 arm,psci-suspend-param = <0x4100c344>;
325 entry-latency-us = <2800>;
326 exit-latency-us = <4400>;
327 min-residency-us = <10150>;
334 compatible = "qcom,scm-sm8550", "qcom,scm";
339 clk_virt: interconnect-0 {
340 compatible = "qcom,sm8550-clk-virt";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
345 mc_virt: interconnect-1 {
346 compatible = "qcom,sm8550-mc-virt";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
358 compatible = "arm,armv8-pmuv3";
363 compatible = "arm,psci-1.0";
366 CPU_PD0: power-domain-cpu0 {
367 #power-domain-cells = <0>;
368 power-domains = <&CLUSTER_PD>;
369 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
372 CPU_PD1: power-domain-cpu1 {
373 #power-domain-cells = <0>;
374 power-domains = <&CLUSTER_PD>;
375 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
378 CPU_PD2: power-domain-cpu2 {
379 #power-domain-cells = <0>;
380 power-domains = <&CLUSTER_PD>;
381 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
384 CPU_PD3: power-domain-cpu3 {
385 #power-domain-cells = <0>;
386 power-domains = <&CLUSTER_PD>;
387 domain-idle-states = <&BIG_CPU_SLEEP_0>;
390 CPU_PD4: power-domain-cpu4 {
391 #power-domain-cells = <0>;
392 power-domains = <&CLUSTER_PD>;
393 domain-idle-states = <&BIG_CPU_SLEEP_0>;
396 CPU_PD5: power-domain-cpu5 {
397 #power-domain-cells = <0>;
398 power-domains = <&CLUSTER_PD>;
399 domain-idle-states = <&BIG_CPU_SLEEP_0>;
402 CPU_PD6: power-domain-cpu6 {
403 #power-domain-cells = <0>;
404 power-domains = <&CLUSTER_PD>;
405 domain-idle-states = <&BIG_CPU_SLEEP_0>;
408 CPU_PD7: power-domain-cpu7 {
409 #power-domain-cells = <0>;
410 power-domains = <&CLUSTER_PD>;
411 domain-idle-states = <&PRIME_CPU_SLEEP_0>;
414 CLUSTER_PD: power-domain-cluster {
415 #power-domain-cells = <0>;
416 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
420 reserved_memory: reserved-memory {
421 #address-cells = <2>;
422 #size-cells = <2>;
425 hyp_mem: hyp-region@80000000 {
427 no-map;
430 cpusys_vm_mem: cpusys-vm-region@80a00000 {
432 no-map;
435 hyp_tags_mem: hyp-tags-region@80e00000 {
437 no-map;
440 xbl_sc_mem: xbl-sc-region@d8100000 {
442 no-map;
445 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
447 no-map;
451 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
453 no-map;
456 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
457 compatible = "qcom,cmd-db";
459 no-map;
463 aop_config_merged_mem: aop-config-merged-region@81c80000 {
465 no-map;
473 no-map;
476 adsp_mhi_mem: adsp-mhi-region@81f00000 {
478 no-map;
481 global_sync_mem: global-sync-region@82600000 {
483 no-map;
486 tz_stat_mem: tz-stat-region@82700000 {
488 no-map;
491 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
493 no-map;
496 mpss_mem: mpss-region@8a800000 {
498 no-map;
501 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
503 no-map;
506 ipa_fw_mem: ipa-fw-region@9b080000 {
508 no-map;
511 ipa_gsi_mem: ipa-gsi-region@9b090000 {
513 no-map;
516 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
518 no-map;
521 spss_region_mem: spss-region@9b100000 {
523 no-map;
527 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
529 no-map;
533 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
535 no-map;
538 camera_mem: camera-region@9b300000 {
540 no-map;
543 video_mem: video-region@9bb00000 {
545 no-map;
548 cvp_mem: cvp-region@9c200000 {
550 no-map;
553 cdsp_mem: cdsp-region@9c900000 {
555 no-map;
558 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
560 no-map;
563 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
565 no-map;
568 adspslpi_mem: adspslpi-region@9ea00000 {
570 no-map;
577 rmtfs_mem: rmtfs-region@d4a80000 {
578 compatible = "qcom,rmtfs-mem";
580 no-map;
582 qcom,client-id = <1>;
586 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
588 no-map;
591 tz_reserved_mem: tz-reserved-region@d8000000 {
593 no-map;
596 cpucp_fw_mem: cpucp-fw-region@d8140000 {
598 no-map;
601 qtee_mem: qtee-region@d8300000 {
603 no-map;
606 ta_mem: ta-region@d8800000 {
608 no-map;
611 tz_tags_mem: tz-tags-region@e1200000 {
613 no-map;
616 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
618 no-map;
621 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
623 no-map;
626 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
628 no-map;
631 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
633 no-map;
636 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
638 no-map;
641 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
643 no-map;
646 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
648 no-map;
651 oem_vm_mem: oem-vm-region@f8400000 {
653 no-map;
656 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
658 no-map;
661 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
663 no-map;
666 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
668 no-map;
671 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
673 no-map;
677 smp2p-adsp {
680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
686 qcom,local-pid = <0>;
687 qcom,remote-pid = <2>;
689 smp2p_adsp_out: master-kernel {
690 qcom,entry-name = "master-kernel";
691 #qcom,smem-state-cells = <1>;
694 smp2p_adsp_in: slave-kernel {
695 qcom,entry-name = "slave-kernel";
696 interrupt-controller;
697 #interrupt-cells = <2>;
701 smp2p-cdsp {
704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
710 qcom,local-pid = <0>;
711 qcom,remote-pid = <5>;
713 smp2p_cdsp_out: master-kernel {
714 qcom,entry-name = "master-kernel";
715 #qcom,smem-state-cells = <1>;
718 smp2p_cdsp_in: slave-kernel {
719 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 smp2p-modem {
728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <1>;
737 smp2p_modem_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 smp2p_modem_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
748 ipa_smp2p_out: ipa-ap-to-modem {
749 qcom,entry-name = "ipa";
750 #qcom,smem-state-cells = <1>;
753 ipa_smp2p_in: ipa-modem-to-ap {
754 qcom,entry-name = "ipa";
755 interrupt-controller;
756 #interrupt-cells = <2>;
761 compatible = "simple-bus";
763 dma-ranges = <0 0 0 0 0x10 0>;
765 #address-cells = <2>;
766 #size-cells = <2>;
768 gcc: clock-controller@100000 {
769 compatible = "qcom,sm8550-gcc";
771 #clock-cells = <1>;
772 #reset-cells = <1>;
773 #power-domain-cells = <1>;
785 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
788 interrupt-controller;
789 #interrupt-cells = <3>;
790 #mbox-cells = <2>;
793 gpi_dma2: dma-controller@800000 {
794 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
795 #dma-cells = <3>;
809 dma-channels = <12>;
810 dma-channel-mask = <0x3e>;
816 compatible = "qcom,geni-se-qup";
819 clock-names = "m-ahb", "s-ahb";
823 #address-cells = <2>;
824 #size-cells = <2>;
828 compatible = "qcom,geni-i2c";
830 clock-names = "se";
832 pinctrl-names = "default";
833 pinctrl-0 = <&qup_i2c8_data_clk>;
835 #address-cells = <1>;
836 #size-cells = <0>;
840 interconnect-names = "qup-core", "qup-config", "qup-memory";
843 dma-names = "tx", "rx";
848 compatible = "qcom,geni-spi";
850 clock-names = "se";
853 pinctrl-names = "default";
854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
858 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dma-names = "tx", "rx";
862 #address-cells = <1>;
863 #size-cells = <0>;
868 compatible = "qcom,geni-i2c";
870 clock-names = "se";
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_i2c9_data_clk>;
875 #address-cells = <1>;
876 #size-cells = <0>;
880 interconnect-names = "qup-core", "qup-config", "qup-memory";
883 dma-names = "tx", "rx";
888 compatible = "qcom,geni-spi";
890 clock-names = "se";
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
898 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 dma-names = "tx", "rx";
902 #address-cells = <1>;
903 #size-cells = <0>;
908 compatible = "qcom,geni-i2c";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_i2c10_data_clk>;
915 #address-cells = <1>;
916 #size-cells = <0>;
920 interconnect-names = "qup-core", "qup-config", "qup-memory";
923 dma-names = "tx", "rx";
928 compatible = "qcom,geni-spi";
930 clock-names = "se";
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
941 dma-names = "tx", "rx";
942 #address-cells = <1>;
943 #size-cells = <0>;
948 compatible = "qcom,geni-i2c";
950 clock-names = "se";
952 pinctrl-names = "default";
953 pinctrl-0 = <&qup_i2c11_data_clk>;
955 #address-cells = <1>;
956 #size-cells = <0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
963 dma-names = "tx", "rx";
968 compatible = "qcom,geni-spi";
970 clock-names = "se";
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
978 interconnect-names = "qup-core", "qup-config", "qup-memory";
981 dma-names = "tx", "rx";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c12_data_clk>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1003 dma-names = "tx", "rx";
1008 compatible = "qcom,geni-spi";
1010 clock-names = "se";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1018 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 dma-names = "tx", "rx";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-i2c";
1030 clock-names = "se";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_i2c13_data_clk>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1040 interconnect-names = "qup-core", "qup-config", "qup-memory";
1043 dma-names = "tx", "rx";
1048 compatible = "qcom,geni-spi";
1050 clock-names = "se";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1058 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 dma-names = "tx", "rx";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c15_data_clk>;
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1083 dma-names = "tx", "rx";
1088 compatible = "qcom,geni-spi";
1090 clock-names = "se";
1093 pinctrl-names = "default";
1094 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1098 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 dma-names = "tx", "rx";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1109 compatible = "qcom,geni-se-i2c-master-hub";
1111 clock-names = "s-ahb";
1113 #address-cells = <2>;
1114 #size-cells = <2>;
1119 compatible = "qcom,geni-i2c-master-hub";
1121 clock-names = "se", "core";
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&hub_i2c0_data_clk>;
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1131 interconnect-names = "qup-core", "qup-config";
1136 compatible = "qcom,geni-i2c-master-hub";
1138 clock-names = "se", "core";
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&hub_i2c1_data_clk>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1148 interconnect-names = "qup-core", "qup-config";
1153 compatible = "qcom,geni-i2c-master-hub";
1155 clock-names = "se", "core";
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&hub_i2c2_data_clk>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1165 interconnect-names = "qup-core", "qup-config";
1170 compatible = "qcom,geni-i2c-master-hub";
1172 clock-names = "se", "core";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&hub_i2c3_data_clk>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1182 interconnect-names = "qup-core", "qup-config";
1187 compatible = "qcom,geni-i2c-master-hub";
1189 clock-names = "se", "core";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&hub_i2c4_data_clk>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1199 interconnect-names = "qup-core", "qup-config";
1204 compatible = "qcom,geni-i2c-master-hub";
1206 clock-names = "se", "core";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&hub_i2c5_data_clk>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1216 interconnect-names = "qup-core", "qup-config";
1221 compatible = "qcom,geni-i2c-master-hub";
1223 clock-names = "se", "core";
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&hub_i2c6_data_clk>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1233 interconnect-names = "qup-core", "qup-config";
1238 compatible = "qcom,geni-i2c-master-hub";
1240 clock-names = "se", "core";
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&hub_i2c7_data_clk>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1250 interconnect-names = "qup-core", "qup-config";
1255 compatible = "qcom,geni-i2c-master-hub";
1257 clock-names = "se", "core";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&hub_i2c8_data_clk>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1267 interconnect-names = "qup-core", "qup-config";
1272 compatible = "qcom,geni-i2c-master-hub";
1274 clock-names = "se", "core";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&hub_i2c9_data_clk>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1284 interconnect-names = "qup-core", "qup-config";
1289 gpi_dma1: dma-controller@a00000 {
1290 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1291 #dma-cells = <3>;
1305 dma-channels = <12>;
1306 dma-channel-mask = <0x1e>;
1312 compatible = "qcom,geni-se-qup";
1315 clock-names = "m-ahb", "s-ahb";
1320 interconnect-names = "qup-core";
1321 #address-cells = <2>;
1322 #size-cells = <2>;
1326 compatible = "qcom,geni-i2c";
1328 clock-names = "se";
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&qup_i2c0_data_clk>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1338 interconnect-names = "qup-core", "qup-config", "qup-memory";
1341 dma-names = "tx", "rx";
1346 compatible = "qcom,geni-spi";
1348 clock-names = "se";
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1356 interconnect-names = "qup-core", "qup-config", "qup-memory";
1359 dma-names = "tx", "rx";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "qcom,geni-i2c";
1368 clock-names = "se";
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_i2c1_data_clk>;
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1378 interconnect-names = "qup-core", "qup-config", "qup-memory";
1381 dma-names = "tx", "rx";
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1396 interconnect-names = "qup-core", "qup-config", "qup-memory";
1399 dma-names = "tx", "rx";
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1406 compatible = "qcom,geni-i2c";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c2_data_clk>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1421 dma-names = "tx", "rx";
1426 compatible = "qcom,geni-spi";
1428 clock-names = "se";
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1436 interconnect-names = "qup-core", "qup-config", "qup-memory";
1439 dma-names = "tx", "rx";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 dma-names = "tx", "rx";
1466 compatible = "qcom,geni-spi";
1468 clock-names = "se";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1479 dma-names = "tx", "rx";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1486 compatible = "qcom,geni-i2c";
1488 clock-names = "se";
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 dma-names = "tx", "rx";
1506 compatible = "qcom,geni-spi";
1508 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1516 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 dma-names = "tx", "rx";
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1526 compatible = "qcom,geni-i2c";
1528 clock-names = "se";
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_i2c5_data_clk>;
1536 interconnect-names = "qup-core", "qup-config", "qup-memory";
1539 dma-names = "tx", "rx";
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-spi";
1548 clock-names = "se";
1551 pinctrl-names = "default";
1552 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1559 dma-names = "tx", "rx";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1566 compatible = "qcom,geni-i2c";
1568 clock-names = "se";
1570 pinctrl-names = "default";
1571 pinctrl-0 = <&qup_i2c6_data_clk>;
1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 dma-names = "tx", "rx";
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1586 compatible = "qcom,geni-spi";
1588 clock-names = "se";
1591 pinctrl-names = "default";
1592 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1596 interconnect-names = "qup-core", "qup-config", "qup-memory";
1599 dma-names = "tx", "rx";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 compatible = "qcom,geni-debug-uart";
1608 clock-names = "se";
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&qup_uart7_default>;
1613 interconnect-names = "qup-core", "qup-config";
1621 compatible = "qcom,sm8550-cnoc-main";
1623 #interconnect-cells = <2>;
1624 qcom,bcm-voters = <&apps_bcm_voter>;
1628 compatible = "qcom,sm8550-config-noc";
1630 #interconnect-cells = <2>;
1631 qcom,bcm-voters = <&apps_bcm_voter>;
1635 compatible = "qcom,sm8550-system-noc";
1637 #interconnect-cells = <2>;
1638 qcom,bcm-voters = <&apps_bcm_voter>;
1642 compatible = "qcom,sm8550-pcie-anoc";
1644 #interconnect-cells = <2>;
1647 qcom,bcm-voters = <&apps_bcm_voter>;
1651 compatible = "qcom,sm8550-aggre1-noc";
1653 #interconnect-cells = <2>;
1656 qcom,bcm-voters = <&apps_bcm_voter>;
1660 compatible = "qcom,sm8550-aggre2-noc";
1662 #interconnect-cells = <2>;
1664 qcom,bcm-voters = <&apps_bcm_voter>;
1668 compatible = "qcom,sm8550-mmss-noc";
1670 #interconnect-cells = <2>;
1671 qcom,bcm-voters = <&apps_bcm_voter>;
1676 compatible = "qcom,pcie-sm8550";
1682 reg-names = "parf", "dbi", "elbi", "atu", "config";
1683 #address-cells = <3>;
1684 #size-cells = <2>;
1687 bus-range = <0x00 0xff>;
1689 dma-coherent;
1691 linux,pci-domain = <0>;
1692 num-lanes = <2>;
1695 interrupt-names = "msi";
1697 #interrupt-cells = <1>;
1698 interrupt-map-mask = <0 0 0 0x7>;
1699 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1711 clock-names = "aux",
1721 interconnect-names = "pcie-mem", "cpu-pcie";
1723 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1727 reset-names = "pci";
1729 power-domains = <&gcc PCIE_0_GDSC>;
1732 phy-names = "pciephy";
1738 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1746 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1750 reset-names = "phy";
1752 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1753 assigned-clock-rates = <100000000>;
1755 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1757 #clock-cells = <0>;
1758 clock-output-names = "pcie0_pipe_clk";
1760 #phy-cells = <0>;
1767 compatible = "qcom,pcie-sm8550";
1773 reg-names = "parf", "dbi", "elbi", "atu", "config";
1774 #address-cells = <3>;
1775 #size-cells = <2>;
1778 bus-range = <0x00 0xff>;
1780 dma-coherent;
1782 linux,pci-domain = <1>;
1783 num-lanes = <2>;
1786 interrupt-names = "msi";
1788 #interrupt-cells = <1>;
1789 interrupt-map-mask = <0 0 0 0x7>;
1790 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1803 clock-names = "aux",
1812 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1813 assigned-clock-rates = <19200000>;
1817 interconnect-names = "pcie-mem", "cpu-pcie";
1819 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1824 reset-names = "pci", "link_down";
1826 power-domains = <&gcc PCIE_1_GDSC>;
1829 phy-names = "pciephy";
1835 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1843 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1848 reset-names = "phy", "phy_nocsr";
1850 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1851 assigned-clock-rates = <100000000>;
1853 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1855 #clock-cells = <0>;
1856 clock-output-names = "pcie1_pipe_clk";
1858 #phy-cells = <0>;
1863 cryptobam: dma-controller@1dc4000 {
1864 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1867 #dma-cells = <1>;
1869 qcom,num-ees = <4>;
1870 num-channels = <20>;
1871 qcom,controlled-remotely;
1877 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1880 dma-names = "rx", "tx";
1884 interconnect-names = "memory";
1888 compatible = "qcom,sm8550-qmp-ufs-phy";
1892 clock-names = "ref", "ref_aux";
1894 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1897 reset-names = "ufsphy";
1899 #clock-cells = <1>;
1900 #phy-cells = <0>;
1906 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1907 "jedec,ufs-2.0";
1911 phy-names = "ufsphy";
1912 lanes-per-direction = <2>;
1913 #reset-cells = <1>;
1915 reset-names = "rst";
1917 power-domains = <&gcc UFS_PHY_GDSC>;
1918 required-opps = <&rpmhpd_opp_nom>;
1921 dma-coherent;
1926 interconnect-names = "ufs-ddr", "cpu-ufs";
1927 clock-names = "core_clk",
1943 freq-table-hz =
1958 compatible = "qcom,sm8550-inline-crypto-engine",
1959 "qcom,inline-crypto-engine";
1965 compatible = "qcom,tcsr-mutex";
1967 #hwlock-cells = <1>;
1970 tcsr: clock-controller@1fc0000 {
1971 compatible = "qcom,sm8550-tcsr", "syscon";
1974 #clock-cells = <1>;
1975 #reset-cells = <1>;
1978 gpucc: clock-controller@3d90000 {
1979 compatible = "qcom,sm8550-gpucc";
1984 #clock-cells = <1>;
1985 #reset-cells = <1>;
1986 #power-domain-cells = <1>;
1990 compatible = "qcom,sm8550-mpss-pas";
1993 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
1999 interrupt-names = "wdog", "fatal", "ready", "handover",
2000 "stop-ack", "shutdown-ack";
2003 clock-names = "xo";
2005 power-domains = <&rpmhpd RPMHPD_CX>,
2007 power-domain-names = "cx", "mss";
2011 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2015 qcom,smem-states = <&smp2p_modem_out 0>;
2016 qcom,smem-state-names = "stop";
2020 glink-edge {
2021 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2027 qcom,remote-pid = <1>;
2032 compatible = "qcom,sm8550-adsp-pas";
2035 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2040 interrupt-names = "wdog", "fatal", "ready",
2041 "handover", "stop-ack";
2044 clock-names = "xo";
2046 power-domains = <&rpmhpd RPMHPD_LCX>,
2048 power-domain-names = "lcx", "lmx";
2052 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2056 qcom,smem-states = <&smp2p_adsp_out 0>;
2057 qcom,smem-state-names = "stop";
2061 remoteproc_adsp_glink: glink-edge {
2062 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2069 qcom,remote-pid = <2>;
2073 qcom,glink-channels = "fastrpcglink-apps-dsp";
2075 qcom,non-secure-domain;
2076 #address-cells = <1>;
2077 #size-cells = <0>;
2079 compute-cb@3 {
2080 compatible = "qcom,fastrpc-compute-cb";
2084 dma-coherent;
2087 compute-cb@4 {
2088 compatible = "qcom,fastrpc-compute-cb";
2092 dma-coherent;
2095 compute-cb@5 {
2096 compatible = "qcom,fastrpc-compute-cb";
2100 dma-coherent;
2103 compute-cb@6 {
2104 compatible = "qcom,fastrpc-compute-cb";
2108 dma-coherent;
2111 compute-cb@7 {
2112 compatible = "qcom,fastrpc-compute-cb";
2116 dma-coherent;
2122 qcom,glink-channels = "adsp_apps";
2125 #address-cells = <1>;
2126 #size-cells = <0>;
2131 #sound-dai-cells = <0>;
2132 qcom,protection-domain = "avs/audio",
2136 compatible = "qcom,q6apm-dais";
2142 compatible = "qcom,q6apm-lpass-dais";
2143 #sound-dai-cells = <1>;
2150 qcom,protection-domain = "avs/audio",
2153 q6prmcc: clock-controller {
2154 compatible = "qcom,q6prm-lpass-clocks";
2155 #clock-cells = <2>;
2163 compatible = "qcom,sm8550-lpass-wsa-macro";
2169 clock-names = "mclk", "macro", "dcodec", "fsgen";
2170 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2171 assigned-clock-rates = <19200000>;
2173 #clock-cells = <0>;
2174 clock-output-names = "wsa2-mclk";
2175 pinctrl-names = "default";
2176 pinctrl-0 = <&wsa2_swr_active>;
2177 #sound-dai-cells = <1>;
2181 compatible = "qcom,soundwire-v2.0.0";
2185 clock-names = "iface";
2188 qcom,din-ports = <4>;
2189 qcom,dout-ports = <9>;
2191 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2192 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2193 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2194 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2195 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2196 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2197 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2198 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2199 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2201 #address-cells = <2>;
2202 #size-cells = <0>;
2203 #sound-dai-cells = <1>;
2208 compatible = "qcom,sm8550-lpass-rx-macro";
2214 clock-names = "mclk", "macro", "dcodec", "fsgen";
2216 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2217 assigned-clock-rates = <19200000>;
2219 #clock-cells = <0>;
2220 clock-output-names = "mclk";
2221 pinctrl-names = "default";
2222 pinctrl-0 = <&rx_swr_active>;
2223 #sound-dai-cells = <1>;
2227 compatible = "qcom,soundwire-v2.0.0";
2231 clock-names = "iface";
2234 qcom,din-ports = <0>;
2235 qcom,dout-ports = <10>;
2237 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2238 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2239 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2240 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2241 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2242 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2243 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2244 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2245 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2247 #address-cells = <2>;
2248 #size-cells = <0>;
2249 #sound-dai-cells = <1>;
2254 compatible = "qcom,sm8550-lpass-tx-macro";
2260 clock-names = "mclk", "macro", "dcodec", "fsgen";
2261 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2263 assigned-clock-rates = <19200000>;
2265 #clock-cells = <0>;
2266 clock-output-names = "mclk";
2267 pinctrl-names = "default";
2268 pinctrl-0 = <&tx_swr_active>;
2269 #sound-dai-cells = <1>;
2273 compatible = "qcom,sm8550-lpass-wsa-macro";
2279 clock-names = "mclk", "macro", "dcodec", "fsgen";
2281 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2282 assigned-clock-rates = <19200000>;
2284 #clock-cells = <0>;
2285 clock-output-names = "mclk";
2286 pinctrl-names = "default";
2287 pinctrl-0 = <&wsa_swr_active>;
2288 #sound-dai-cells = <1>;
2292 compatible = "qcom,soundwire-v2.0.0";
2296 clock-names = "iface";
2299 qcom,din-ports = <4>;
2300 qcom,dout-ports = <9>;
2302 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2303 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2304 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2305 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2306 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2307 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2308 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2309 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2310 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2312 #address-cells = <2>;
2313 #size-cells = <0>;
2314 #sound-dai-cells = <1>;
2319 compatible = "qcom,soundwire-v2.0.0";
2323 interrupt-names = "core", "wakeup";
2325 clock-names = "iface";
2328 qcom,din-ports = <4>;
2329 qcom,dout-ports = <0>;
2330 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2331 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2332 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2333 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2334 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2335 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2336 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2337 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2338 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2340 #address-cells = <2>;
2341 #size-cells = <0>;
2342 #sound-dai-cells = <1>;
2347 compatible = "qcom,sm8550-lpass-va-macro";
2352 clock-names = "mclk", "macro", "dcodec";
2354 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2355 assigned-clock-rates = <19200000>;
2357 #clock-cells = <0>;
2358 clock-output-names = "fsgen";
2359 #sound-dai-cells = <1>;
2363 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2366 gpio-controller;
2367 #gpio-cells = <2>;
2368 gpio-ranges = <&lpass_tlmm 0 0 23>;
2372 clock-names = "core", "audio";
2374 tx_swr_active: tx-swr-active-state {
2375 clk-pins {
2378 drive-strength = <2>;
2379 slew-rate = <1>;
2380 bias-disable;
2383 data-pins {
2386 drive-strength = <2>;
2387 slew-rate = <1>;
2388 bias-bus-hold;
2392 rx_swr_active: rx-swr-active-state {
2393 clk-pins {
2396 drive-strength = <2>;
2397 slew-rate = <1>;
2398 bias-disable;
2401 data-pins {
2404 drive-strength = <2>;
2405 slew-rate = <1>;
2406 bias-bus-hold;
2410 dmic01_default: dmic01-default-state {
2411 clk-pins {
2414 drive-strength = <8>;
2415 output-high;
2418 data-pins {
2421 drive-strength = <8>;
2422 input-enable;
2426 dmic02_default: dmic02-default-state {
2427 clk-pins {
2430 drive-strength = <8>;
2431 output-high;
2434 data-pins {
2437 drive-strength = <8>;
2438 input-enable;
2442 wsa_swr_active: wsa-swr-active-state {
2443 clk-pins {
2446 drive-strength = <2>;
2447 slew-rate = <1>;
2448 bias-disable;
2451 data-pins {
2454 drive-strength = <2>;
2455 slew-rate = <1>;
2456 bias-bus-hold;
2460 wsa2_swr_active: wsa2-swr-active-state {
2461 clk-pins {
2464 drive-strength = <2>;
2465 slew-rate = <1>;
2466 bias-disable;
2469 data-pins {
2472 drive-strength = <2>;
2473 slew-rate = <1>;
2474 bias-bus-hold;
2480 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2482 #interconnect-cells = <2>;
2483 qcom,bcm-voters = <&apps_bcm_voter>;
2487 compatible = "qcom,sm8550-lpass-lpicx-noc";
2489 #interconnect-cells = <2>;
2490 qcom,bcm-voters = <&apps_bcm_voter>;
2494 compatible = "qcom,sm8550-lpass-ag-noc";
2496 #interconnect-cells = <2>;
2497 qcom,bcm-voters = <&apps_bcm_voter>;
2501 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2506 interrupt-names = "hc_irq", "pwr_irq";
2511 clock-names = "iface", "core", "xo";
2513 qcom,dll-config = <0x0007642c>;
2514 qcom,ddr-config = <0x80040868>;
2515 power-domains = <&rpmhpd RPMHPD_CX>;
2516 operating-points-v2 = <&sdhc2_opp_table>;
2520 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2521 bus-width = <4>;
2522 dma-coherent;
2524 /* Forbid SDR104/SDR50 - broken hw! */
2525 sdhci-caps-mask = <0x3 0>;
2529 sdhc2_opp_table: opp-table {
2530 compatible = "operating-points-v2";
2532 opp-19200000 {
2533 opp-hz = /bits/ 64 <19200000>;
2534 required-opps = <&rpmhpd_opp_min_svs>;
2537 opp-50000000 {
2538 opp-hz = /bits/ 64 <50000000>;
2539 required-opps = <&rpmhpd_opp_low_svs>;
2542 opp-100000000 {
2543 opp-hz = /bits/ 64 <100000000>;
2544 required-opps = <&rpmhpd_opp_svs>;
2547 opp-202000000 {
2548 opp-hz = /bits/ 64 <202000000>;
2549 required-opps = <&rpmhpd_opp_svs_l1>;
2554 videocc: clock-controller@aaf0000 {
2555 compatible = "qcom,sm8550-videocc";
2559 power-domains = <&rpmhpd RPMHPD_MMCX>;
2560 required-opps = <&rpmhpd_opp_low_svs>;
2561 #clock-cells = <1>;
2562 #reset-cells = <1>;
2563 #power-domain-cells = <1>;
2566 mdss: display-subsystem@ae00000 {
2567 compatible = "qcom,sm8550-mdss";
2569 reg-names = "mdss";
2572 interrupt-controller;
2573 #interrupt-cells = <1>;
2582 power-domains = <&dispcc MDSS_GDSC>;
2585 interconnect-names = "mdp0-mem";
2589 #address-cells = <2>;
2590 #size-cells = <2>;
2595 mdss_mdp: display-controller@ae01000 {
2596 compatible = "qcom,sm8550-dpu";
2599 reg-names = "mdp", "vbif";
2601 interrupt-parent = <&mdss>;
2610 clock-names = "bus",
2617 power-domains = <&rpmhpd RPMHPD_MMCX>;
2619 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2620 assigned-clock-rates = <19200000>;
2622 operating-points-v2 = <&mdp_opp_table>;
2624 ports {
2625 #address-cells = <1>;
2626 #size-cells = <0>;
2631 remote-endpoint = <&mdss_dsi0_in>;
2638 remote-endpoint = <&mdss_dsi1_in>;
2645 remote-endpoint = <&mdss_dp0_in>;
2650 mdp_opp_table: opp-table {
2651 compatible = "operating-points-v2";
2653 opp-200000000 {
2654 opp-hz = /bits/ 64 <200000000>;
2655 required-opps = <&rpmhpd_opp_low_svs>;
2658 opp-325000000 {
2659 opp-hz = /bits/ 64 <325000000>;
2660 required-opps = <&rpmhpd_opp_svs>;
2663 opp-375000000 {
2664 opp-hz = /bits/ 64 <375000000>;
2665 required-opps = <&rpmhpd_opp_svs_l1>;
2668 opp-514000000 {
2669 opp-hz = /bits/ 64 <514000000>;
2670 required-opps = <&rpmhpd_opp_nom>;
2675 mdss_dp0: displayport-controller@ae90000 {
2676 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2682 interrupt-parent = <&mdss>;
2689 clock-names = "core_iface",
2695 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2697 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2701 phy-names = "dp";
2703 #sound-dai-cells = <0>;
2705 operating-points-v2 = <&dp_opp_table>;
2706 power-domains = <&rpmhpd RPMHPD_MMCX>;
2710 ports {
2711 #address-cells = <1>;
2712 #size-cells = <0>;
2717 remote-endpoint = <&dpu_intf0_out>;
2728 dp_opp_table: opp-table {
2729 compatible = "operating-points-v2";
2731 opp-162000000 {
2732 opp-hz = /bits/ 64 <162000000>;
2733 required-opps = <&rpmhpd_opp_low_svs_d1>;
2736 opp-270000000 {
2737 opp-hz = /bits/ 64 <270000000>;
2738 required-opps = <&rpmhpd_opp_low_svs>;
2741 opp-540000000 {
2742 opp-hz = /bits/ 64 <540000000>;
2743 required-opps = <&rpmhpd_opp_svs_l1>;
2746 opp-810000000 {
2747 opp-hz = /bits/ 64 <810000000>;
2748 required-opps = <&rpmhpd_opp_nom>;
2754 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2756 reg-names = "dsi_ctrl";
2758 interrupt-parent = <&mdss>;
2767 clock-names = "byte",
2774 power-domains = <&rpmhpd RPMHPD_MMCX>;
2776 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2778 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2781 operating-points-v2 = <&mdss_dsi_opp_table>;
2784 phy-names = "dsi";
2786 #address-cells = <1>;
2787 #size-cells = <0>;
2791 ports {
2792 #address-cells = <1>;
2793 #size-cells = <0>;
2798 remote-endpoint = <&dpu_intf1_out>;
2809 mdss_dsi_opp_table: opp-table {
2810 compatible = "operating-points-v2";
2812 opp-187500000 {
2813 opp-hz = /bits/ 64 <187500000>;
2814 required-opps = <&rpmhpd_opp_low_svs>;
2817 opp-300000000 {
2818 opp-hz = /bits/ 64 <300000000>;
2819 required-opps = <&rpmhpd_opp_svs>;
2822 opp-358000000 {
2823 opp-hz = /bits/ 64 <358000000>;
2824 required-opps = <&rpmhpd_opp_svs_l1>;
2830 compatible = "qcom,sm8550-dsi-phy-4nm";
2834 reg-names = "dsi_phy",
2840 clock-names = "iface", "ref";
2842 #clock-cells = <1>;
2843 #phy-cells = <0>;
2849 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2851 reg-names = "dsi_ctrl";
2853 interrupt-parent = <&mdss>;
2862 clock-names = "byte",
2869 power-domains = <&rpmhpd RPMHPD_MMCX>;
2871 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2873 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2876 operating-points-v2 = <&mdss_dsi_opp_table>;
2879 phy-names = "dsi";
2881 #address-cells = <1>;
2882 #size-cells = <0>;
2886 ports {
2887 #address-cells = <1>;
2888 #size-cells = <0>;
2893 remote-endpoint = <&dpu_intf2_out>;
2906 compatible = "qcom,sm8550-dsi-phy-4nm";
2910 reg-names = "dsi_phy",
2916 clock-names = "iface", "ref";
2918 #clock-cells = <1>;
2919 #phy-cells = <0>;
2925 dispcc: clock-controller@af00000 {
2926 compatible = "qcom,sm8550-dispcc";
2944 power-domains = <&rpmhpd RPMHPD_MMCX>;
2945 required-opps = <&rpmhpd_opp_low_svs>;
2946 #clock-cells = <1>;
2947 #reset-cells = <1>;
2948 #power-domain-cells = <1>;
2952 compatible = "qcom,sm8550-snps-eusb2-phy";
2954 #phy-cells = <0>;
2957 clock-names = "ref";
2965 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2972 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2974 power-domains = <&gcc USB3_PHY_GDSC>;
2978 reset-names = "phy", "common";
2980 #clock-cells = <1>;
2981 #phy-cells = <1>;
2985 ports {
2986 #address-cells = <1>;
2987 #size-cells = <0>;
3013 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3015 #address-cells = <2>;
3016 #size-cells = <2>;
3025 clock-names = "cfg_noc",
3032 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3034 assigned-clock-rates = <19200000>, <200000000>;
3036 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3040 interrupt-names = "hs_phy_irq",
3045 power-domains = <&gcc USB30_PRIM_GDSC>;
3046 required-opps = <&rpmhpd_opp_nom>;
3052 interconnect-names = "usb-ddr", "apps-usb";
3066 phy-names = "usb2-phy", "usb3-phy";
3068 ports {
3069 #address-cells = <1>;
3070 #size-cells = <0>;
3089 pdc: interrupt-controller@b220000 {
3090 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3092 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3095 #interrupt-cells = <2>;
3096 interrupt-parent = <&intc>;
3097 interrupt-controller;
3100 tsens0: thermal-sensor@c271000 {
3101 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3107 interrupt-names = "uplow", "critical";
3108 #thermal-sensor-cells = <1>;
3111 tsens1: thermal-sensor@c272000 {
3112 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3118 interrupt-names = "uplow", "critical";
3119 #thermal-sensor-cells = <1>;
3122 tsens2: thermal-sensor@c273000 {
3123 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3129 interrupt-names = "uplow", "critical";
3130 #thermal-sensor-cells = <1>;
3133 aoss_qmp: power-management@c300000 {
3134 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3136 interrupt-parent = <&ipcc>;
3137 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3141 #clock-cells = <0>;
3145 compatible = "qcom,rpmh-stats";
3150 compatible = "qcom,spmi-pmic-arb";
3156 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3157 interrupt-names = "periph_irq";
3158 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3161 qcom,bus-id = <0>;
3162 #address-cells = <2>;
3163 #size-cells = <0>;
3164 interrupt-controller;
3165 #interrupt-cells = <4>;
3169 compatible = "qcom,sm8550-tlmm";
3172 gpio-controller;
3173 #gpio-cells = <2>;
3174 interrupt-controller;
3175 #interrupt-cells = <2>;
3176 gpio-ranges = <&tlmm 0 0 211>;
3177 wakeup-parent = <&pdc>;
3179 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3183 drive-strength = <2>;
3184 bias-pull-up;
3187 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3191 drive-strength = <2>;
3192 bias-pull-up;
3195 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3199 drive-strength = <2>;
3200 bias-pull-up;
3203 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3207 drive-strength = <2>;
3208 bias-pull-up;
3211 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3215 drive-strength = <2>;
3216 bias-pull-up;
3219 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3223 drive-strength = <2>;
3224 bias-pull-up;
3227 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3231 drive-strength = <2>;
3232 bias-pull-up;
3235 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3239 drive-strength = <2>;
3240 bias-pull-up;
3243 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3247 drive-strength = <2>;
3248 bias-pull-up;
3251 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3255 drive-strength = <2>;
3256 bias-pull-up;
3259 pcie0_default_state: pcie0-default-state {
3260 perst-pins {
3263 drive-strength = <2>;
3264 bias-pull-down;
3267 clkreq-pins {
3270 drive-strength = <2>;
3271 bias-pull-up;
3274 wake-pins {
3277 drive-strength = <2>;
3278 bias-pull-up;
3282 pcie1_default_state: pcie1-default-state {
3283 perst-pins {
3286 drive-strength = <2>;
3287 bias-pull-down;
3290 clkreq-pins {
3293 drive-strength = <2>;
3294 bias-pull-up;
3297 wake-pins {
3300 drive-strength = <2>;
3301 bias-pull-up;
3305 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3309 drive-strength = <2>;
3310 bias-pull-up = <2200>;
3313 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3317 drive-strength = <2>;
3318 bias-pull-up = <2200>;
3321 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3325 drive-strength = <2>;
3326 bias-pull-up = <2200>;
3329 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3333 drive-strength = <2>;
3334 bias-pull-up = <2200>;
3337 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3341 drive-strength = <2>;
3342 bias-pull-up = <2200>;
3345 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3349 drive-strength = <2>;
3350 bias-pull-up = <2200>;
3353 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3357 drive-strength = <2>;
3358 bias-pull-up = <2200>;
3361 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3362 scl-pins {
3365 drive-strength = <2>;
3366 bias-pull-up = <2200>;
3369 sda-pins {
3372 drive-strength = <2>;
3373 bias-pull-up = <2200>;
3377 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3381 drive-strength = <2>;
3382 bias-pull-up = <2200>;
3385 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3389 drive-strength = <2>;
3390 bias-pull-up = <2200>;
3393 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3397 drive-strength = <2>;
3398 bias-pull-up = <2200>;
3401 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3405 drive-strength = <2>;
3406 bias-pull-up = <2200>;
3409 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3413 drive-strength = <2>;
3414 bias-pull-up = <2200>;
3417 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3421 drive-strength = <2>;
3422 bias-pull-up = <2200>;
3425 qup_spi0_cs: qup-spi0-cs-state {
3428 drive-strength = <6>;
3429 bias-disable;
3432 qup_spi0_data_clk: qup-spi0-data-clk-state {
3436 drive-strength = <6>;
3437 bias-disable;
3440 qup_spi1_cs: qup-spi1-cs-state {
3443 drive-strength = <6>;
3444 bias-disable;
3447 qup_spi1_data_clk: qup-spi1-data-clk-state {
3451 drive-strength = <6>;
3452 bias-disable;
3455 qup_spi2_cs: qup-spi2-cs-state {
3458 drive-strength = <6>;
3459 bias-disable;
3462 qup_spi2_data_clk: qup-spi2-data-clk-state {
3466 drive-strength = <6>;
3467 bias-disable;
3470 qup_spi3_cs: qup-spi3-cs-state {
3473 drive-strength = <6>;
3474 bias-disable;
3477 qup_spi3_data_clk: qup-spi3-data-clk-state {
3481 drive-strength = <6>;
3482 bias-disable;
3485 qup_spi4_cs: qup-spi4-cs-state {
3488 drive-strength = <6>;
3489 bias-disable;
3492 qup_spi4_data_clk: qup-spi4-data-clk-state {
3496 drive-strength = <6>;
3497 bias-disable;
3500 qup_spi5_cs: qup-spi5-cs-state {
3503 drive-strength = <6>;
3504 bias-disable;
3507 qup_spi5_data_clk: qup-spi5-data-clk-state {
3511 drive-strength = <6>;
3512 bias-disable;
3515 qup_spi6_cs: qup-spi6-cs-state {
3518 drive-strength = <6>;
3519 bias-disable;
3522 qup_spi6_data_clk: qup-spi6-data-clk-state {
3526 drive-strength = <6>;
3527 bias-disable;
3530 qup_spi8_cs: qup-spi8-cs-state {
3533 drive-strength = <6>;
3534 bias-disable;
3537 qup_spi8_data_clk: qup-spi8-data-clk-state {
3541 drive-strength = <6>;
3542 bias-disable;
3545 qup_spi9_cs: qup-spi9-cs-state {
3548 drive-strength = <6>;
3549 bias-disable;
3552 qup_spi9_data_clk: qup-spi9-data-clk-state {
3556 drive-strength = <6>;
3557 bias-disable;
3560 qup_spi10_cs: qup-spi10-cs-state {
3563 drive-strength = <6>;
3564 bias-disable;
3567 qup_spi10_data_clk: qup-spi10-data-clk-state {
3571 drive-strength = <6>;
3572 bias-disable;
3575 qup_spi11_cs: qup-spi11-cs-state {
3578 drive-strength = <6>;
3579 bias-disable;
3582 qup_spi11_data_clk: qup-spi11-data-clk-state {
3586 drive-strength = <6>;
3587 bias-disable;
3590 qup_spi12_cs: qup-spi12-cs-state {
3593 drive-strength = <6>;
3594 bias-disable;
3597 qup_spi12_data_clk: qup-spi12-data-clk-state {
3601 drive-strength = <6>;
3602 bias-disable;
3605 qup_spi13_cs: qup-spi13-cs-state {
3608 drive-strength = <6>;
3609 bias-disable;
3612 qup_spi13_data_clk: qup-spi13-data-clk-state {
3616 drive-strength = <6>;
3617 bias-disable;
3620 qup_spi15_cs: qup-spi15-cs-state {
3623 drive-strength = <6>;
3624 bias-disable;
3627 qup_spi15_data_clk: qup-spi15-data-clk-state {
3631 drive-strength = <6>;
3632 bias-disable;
3635 qup_uart7_default: qup-uart7-default-state {
3639 drive-strength = <2>;
3640 bias-disable;
3643 sdc2_sleep: sdc2-sleep-state {
3644 clk-pins {
3646 bias-disable;
3647 drive-strength = <2>;
3650 cmd-pins {
3652 bias-pull-up;
3653 drive-strength = <2>;
3656 data-pins {
3658 bias-pull-up;
3659 drive-strength = <2>;
3663 sdc2_default: sdc2-default-state {
3664 clk-pins {
3666 bias-disable;
3667 drive-strength = <16>;
3670 cmd-pins {
3672 bias-pull-up;
3673 drive-strength = <10>;
3676 data-pins {
3678 bias-pull-up;
3679 drive-strength = <10>;
3685 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3687 #iommu-cells = <2>;
3688 #global-interrupts = <1>;
3788 intc: interrupt-controller@17100000 {
3789 compatible = "arm,gic-v3";
3793 #interrupt-cells = <3>;
3794 interrupt-controller;
3795 #redistributor-regions = <1>;
3796 redistributor-stride = <0 0x40000>;
3798 #address-cells = <2>;
3799 #size-cells = <2>;
3801 gic_its: msi-controller@17140000 {
3802 compatible = "arm,gic-v3-its";
3804 msi-controller;
3805 #msi-cells = <1>;
3810 compatible = "arm,armv7-timer-mem";
3813 #address-cells = <1>;
3814 #size-cells = <1>;
3819 frame-number = <0>;
3826 frame-number = <1>;
3833 frame-number = <2>;
3840 frame-number = <3>;
3847 frame-number = <4>;
3854 frame-number = <5>;
3861 frame-number = <6>;
3869 compatible = "qcom,rpmh-rsc";
3874 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3878 qcom,tcs-offset = <0xd00>;
3879 qcom,drv-id = <2>;
3880 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3882 power-domains = <&CLUSTER_PD>;
3884 apps_bcm_voter: bcm-voter {
3885 compatible = "qcom,bcm-voter";
3888 rpmhcc: clock-controller {
3889 compatible = "qcom,sm8550-rpmh-clk";
3890 #clock-cells = <1>;
3891 clock-names = "xo";
3895 rpmhpd: power-controller {
3896 compatible = "qcom,sm8550-rpmhpd";
3897 #power-domain-cells = <1>;
3898 operating-points-v2 = <&rpmhpd_opp_table>;
3900 rpmhpd_opp_table: opp-table {
3901 compatible = "operating-points-v2";
3903 rpmhpd_opp_ret: opp-16 {
3904 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3907 rpmhpd_opp_min_svs: opp-48 {
3908 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3911 rpmhpd_opp_low_svs_d2: opp-52 {
3912 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3915 rpmhpd_opp_low_svs_d1: opp-56 {
3916 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3919 rpmhpd_opp_low_svs_d0: opp-60 {
3920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3923 rpmhpd_opp_low_svs: opp-64 {
3924 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3927 rpmhpd_opp_low_svs_l1: opp-80 {
3928 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3931 rpmhpd_opp_svs: opp-128 {
3932 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3935 rpmhpd_opp_svs_l0: opp-144 {
3936 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3939 rpmhpd_opp_svs_l1: opp-192 {
3940 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3943 rpmhpd_opp_nom: opp-256 {
3944 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3947 rpmhpd_opp_nom_l1: opp-320 {
3948 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3951 rpmhpd_opp_nom_l2: opp-336 {
3952 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3955 rpmhpd_opp_turbo: opp-384 {
3956 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3959 rpmhpd_opp_turbo_l1: opp-416 {
3960 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3967 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3971 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3973 clock-names = "xo", "alternate";
3977 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3978 #freq-domain-cells = <1>;
3979 #clock-cells = <1>;
3983 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3988 operating-points-v2 = <&llcc_bwmon_opp_table>;
3990 llcc_bwmon_opp_table: opp-table {
3991 compatible = "operating-points-v2";
3993 opp-0 {
3994 opp-peak-kBps = <2086000>;
3997 opp-1 {
3998 opp-peak-kBps = <2929000>;
4001 opp-2 {
4002 opp-peak-kBps = <5931000>;
4005 opp-3 {
4006 opp-peak-kBps = <6515000>;
4009 opp-4 {
4010 opp-peak-kBps = <7980000>;
4013 opp-5 {
4014 opp-peak-kBps = <10437000>;
4017 opp-6 {
4018 opp-peak-kBps = <12157000>;
4021 opp-7 {
4022 opp-peak-kBps = <14060000>;
4025 opp-8 {
4026 opp-peak-kBps = <16113000>;
4032 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4037 operating-points-v2 = <&cpu_bwmon_opp_table>;
4039 cpu_bwmon_opp_table: opp-table {
4040 compatible = "operating-points-v2";
4042 opp-0 {
4043 opp-peak-kBps = <4577000>;
4046 opp-1 {
4047 opp-peak-kBps = <7110000>;
4050 opp-2 {
4051 opp-peak-kBps = <9155000>;
4054 opp-3 {
4055 opp-peak-kBps = <12298000>;
4058 opp-4 {
4059 opp-peak-kBps = <14236000>;
4062 opp-5 {
4063 opp-peak-kBps = <16265000>;
4069 compatible = "qcom,sm8550-gem-noc";
4071 #interconnect-cells = <2>;
4072 qcom,bcm-voters = <&apps_bcm_voter>;
4075 system-cache-controller@25000000 {
4076 compatible = "qcom,sm8550-llcc";
4082 reg-names = "llcc0_base",
4091 compatible = "qcom,sm8550-nsp-noc";
4093 #interconnect-cells = <2>;
4094 qcom,bcm-voters = <&apps_bcm_voter>;
4098 compatible = "qcom,sm8550-cdsp-pas";
4101 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4106 interrupt-names = "wdog", "fatal", "ready",
4107 "handover", "stop-ack";
4110 clock-names = "xo";
4112 power-domains = <&rpmhpd RPMHPD_CX>,
4115 power-domain-names = "cx", "mxc", "nsp";
4119 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4123 qcom,smem-states = <&smp2p_cdsp_out 0>;
4124 qcom,smem-state-names = "stop";
4128 glink-edge {
4129 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4136 qcom,remote-pid = <5>;
4140 qcom,glink-channels = "fastrpcglink-apps-dsp";
4142 qcom,non-secure-domain;
4143 #address-cells = <1>;
4144 #size-cells = <0>;
4146 compute-cb@1 {
4147 compatible = "qcom,fastrpc-compute-cb";
4152 dma-coherent;
4155 compute-cb@2 {
4156 compatible = "qcom,fastrpc-compute-cb";
4161 dma-coherent;
4164 compute-cb@3 {
4165 compatible = "qcom,fastrpc-compute-cb";
4170 dma-coherent;
4173 compute-cb@4 {
4174 compatible = "qcom,fastrpc-compute-cb";
4179 dma-coherent;
4182 compute-cb@5 {
4183 compatible = "qcom,fastrpc-compute-cb";
4188 dma-coherent;
4191 compute-cb@6 {
4192 compatible = "qcom,fastrpc-compute-cb";
4197 dma-coherent;
4200 compute-cb@7 {
4201 compatible = "qcom,fastrpc-compute-cb";
4206 dma-coherent;
4209 compute-cb@8 {
4210 compatible = "qcom,fastrpc-compute-cb";
4215 dma-coherent;
4224 thermal-zones {
4225 aoss0-thermal {
4226 polling-delay-passive = <0>;
4227 polling-delay = <0>;
4228 thermal-sensors = <&tsens0 0>;
4231 thermal-engine-config {
4237 reset-mon-config {
4245 cpuss0-thermal {
4246 polling-delay-passive = <0>;
4247 polling-delay = <0>;
4248 thermal-sensors = <&tsens0 1>;
4251 thermal-engine-config {
4257 reset-mon-config {
4265 cpuss1-thermal {
4266 polling-delay-passive = <0>;
4267 polling-delay = <0>;
4268 thermal-sensors = <&tsens0 2>;
4271 thermal-engine-config {
4277 reset-mon-config {
4285 cpuss2-thermal {
4286 polling-delay-passive = <0>;
4287 polling-delay = <0>;
4288 thermal-sensors = <&tsens0 3>;
4291 thermal-engine-config {
4297 reset-mon-config {
4305 cpuss3-thermal {
4306 polling-delay-passive = <0>;
4307 polling-delay = <0>;
4308 thermal-sensors = <&tsens0 4>;
4311 thermal-engine-config {
4317 reset-mon-config {
4325 cpu3-top-thermal {
4326 polling-delay-passive = <0>;
4327 polling-delay = <0>;
4328 thermal-sensors = <&tsens0 5>;
4331 cpu3_top_alert0: trip-point0 {
4337 cpu3_top_alert1: trip-point1 {
4343 cpu3_top_crit: cpu-critical {
4351 cpu3-bottom-thermal {
4352 polling-delay-passive = <0>;
4353 polling-delay = <0>;
4354 thermal-sensors = <&tsens0 6>;
4357 cpu3_bottom_alert0: trip-point0 {
4363 cpu3_bottom_alert1: trip-point1 {
4369 cpu3_bottom_crit: cpu-critical {
4377 cpu4-top-thermal {
4378 polling-delay-passive = <0>;
4379 polling-delay = <0>;
4380 thermal-sensors = <&tsens0 7>;
4383 cpu4_top_alert0: trip-point0 {
4389 cpu4_top_alert1: trip-point1 {
4395 cpu4_top_crit: cpu-critical {
4403 cpu4-bottom-thermal {
4404 polling-delay-passive = <0>;
4405 polling-delay = <0>;
4406 thermal-sensors = <&tsens0 8>;
4409 cpu4_bottom_alert0: trip-point0 {
4415 cpu4_bottom_alert1: trip-point1 {
4421 cpu4_bottom_crit: cpu-critical {
4429 cpu5-top-thermal {
4430 polling-delay-passive = <0>;
4431 polling-delay = <0>;
4432 thermal-sensors = <&tsens0 9>;
4435 cpu5_top_alert0: trip-point0 {
4441 cpu5_top_alert1: trip-point1 {
4447 cpu5_top_crit: cpu-critical {
4455 cpu5-bottom-thermal {
4456 polling-delay-passive = <0>;
4457 polling-delay = <0>;
4458 thermal-sensors = <&tsens0 10>;
4461 cpu5_bottom_alert0: trip-point0 {
4467 cpu5_bottom_alert1: trip-point1 {
4473 cpu5_bottom_crit: cpu-critical {
4481 cpu6-top-thermal {
4482 polling-delay-passive = <0>;
4483 polling-delay = <0>;
4484 thermal-sensors = <&tsens0 11>;
4487 cpu6_top_alert0: trip-point0 {
4493 cpu6_top_alert1: trip-point1 {
4499 cpu6_top_crit: cpu-critical {
4507 cpu6-bottom-thermal {
4508 polling-delay-passive = <0>;
4509 polling-delay = <0>;
4510 thermal-sensors = <&tsens0 12>;
4513 cpu6_bottom_alert0: trip-point0 {
4519 cpu6_bottom_alert1: trip-point1 {
4525 cpu6_bottom_crit: cpu-critical {
4533 cpu7-top-thermal {
4534 polling-delay-passive = <0>;
4535 polling-delay = <0>;
4536 thermal-sensors = <&tsens0 13>;
4539 cpu7_top_alert0: trip-point0 {
4545 cpu7_top_alert1: trip-point1 {
4551 cpu7_top_crit: cpu-critical {
4559 cpu7-middle-thermal {
4560 polling-delay-passive = <0>;
4561 polling-delay = <0>;
4562 thermal-sensors = <&tsens0 14>;
4565 cpu7_middle_alert0: trip-point0 {
4571 cpu7_middle_alert1: trip-point1 {
4577 cpu7_middle_crit: cpu-critical {
4585 cpu7-bottom-thermal {
4586 polling-delay-passive = <0>;
4587 polling-delay = <0>;
4588 thermal-sensors = <&tsens0 15>;
4591 cpu7_bottom_alert0: trip-point0 {
4597 cpu7_bottom_alert1: trip-point1 {
4603 cpu7_bottom_crit: cpu-critical {
4611 aoss1-thermal {
4612 polling-delay-passive = <0>;
4613 polling-delay = <0>;
4614 thermal-sensors = <&tsens1 0>;
4617 thermal-engine-config {
4623 reset-mon-config {
4631 cpu0-thermal {
4632 polling-delay-passive = <0>;
4633 polling-delay = <0>;
4634 thermal-sensors = <&tsens1 1>;
4637 cpu0_alert0: trip-point0 {
4643 cpu0_alert1: trip-point1 {
4649 cpu0_crit: cpu-critical {
4657 cpu1-thermal {
4658 polling-delay-passive = <0>;
4659 polling-delay = <0>;
4660 thermal-sensors = <&tsens1 2>;
4663 cpu1_alert0: trip-point0 {
4669 cpu1_alert1: trip-point1 {
4675 cpu1_crit: cpu-critical {
4683 cpu2-thermal {
4684 polling-delay-passive = <0>;
4685 polling-delay = <0>;
4686 thermal-sensors = <&tsens1 3>;
4689 cpu2_alert0: trip-point0 {
4695 cpu2_alert1: trip-point1 {
4701 cpu2_crit: cpu-critical {
4709 cdsp0-thermal {
4710 polling-delay-passive = <10>;
4711 polling-delay = <0>;
4712 thermal-sensors = <&tsens2 4>;
4715 thermal-engine-config {
4721 thermal-hal-config {
4727 reset-mon-config {
4733 cdsp0_junction_config: junction-config {
4741 cdsp1-thermal {
4742 polling-delay-passive = <10>;
4743 polling-delay = <0>;
4744 thermal-sensors = <&tsens2 5>;
4747 thermal-engine-config {
4753 thermal-hal-config {
4759 reset-mon-config {
4765 cdsp1_junction_config: junction-config {
4773 cdsp2-thermal {
4774 polling-delay-passive = <10>;
4775 polling-delay = <0>;
4776 thermal-sensors = <&tsens2 6>;
4779 thermal-engine-config {
4785 thermal-hal-config {
4791 reset-mon-config {
4797 cdsp2_junction_config: junction-config {
4805 cdsp3-thermal {
4806 polling-delay-passive = <10>;
4807 polling-delay = <0>;
4808 thermal-sensors = <&tsens2 7>;
4811 thermal-engine-config {
4817 thermal-hal-config {
4823 reset-mon-config {
4829 cdsp3_junction_config: junction-config {
4837 video-thermal {
4838 polling-delay-passive = <0>;
4839 polling-delay = <0>;
4840 thermal-sensors = <&tsens1 8>;
4843 thermal-engine-config {
4849 reset-mon-config {
4857 mem-thermal {
4858 polling-delay-passive = <10>;
4859 polling-delay = <0>;
4860 thermal-sensors = <&tsens1 9>;
4863 thermal-engine-config {
4869 ddr_config0: ddr0-config {
4875 reset-mon-config {
4883 modem0-thermal {
4884 polling-delay-passive = <0>;
4885 polling-delay = <0>;
4886 thermal-sensors = <&tsens1 10>;
4889 thermal-engine-config {
4895 mdmss0_config0: mdmss0-config0 {
4901 mdmss0_config1: mdmss0-config1 {
4907 reset-mon-config {
4915 modem1-thermal {
4916 polling-delay-passive = <0>;
4917 polling-delay = <0>;
4918 thermal-sensors = <&tsens1 11>;
4921 thermal-engine-config {
4927 mdmss1_config0: mdmss1-config0 {
4933 mdmss1_config1: mdmss1-config1 {
4939 reset-mon-config {
4947 modem2-thermal {
4948 polling-delay-passive = <0>;
4949 polling-delay = <0>;
4950 thermal-sensors = <&tsens1 12>;
4953 thermal-engine-config {
4959 mdmss2_config0: mdmss2-config0 {
4965 mdmss2_config1: mdmss2-config1 {
4971 reset-mon-config {
4979 modem3-thermal {
4980 polling-delay-passive = <0>;
4981 polling-delay = <0>;
4982 thermal-sensors = <&tsens1 13>;
4985 thermal-engine-config {
4991 mdmss3_config0: mdmss3-config0 {
4997 mdmss3_config1: mdmss3-config1 {
5003 reset-mon-config {
5011 camera0-thermal {
5012 polling-delay-passive = <0>;
5013 polling-delay = <0>;
5014 thermal-sensors = <&tsens1 14>;
5017 thermal-engine-config {
5023 reset-mon-config {
5031 camera1-thermal {
5032 polling-delay-passive = <0>;
5033 polling-delay = <0>;
5034 thermal-sensors = <&tsens1 15>;
5037 thermal-engine-config {
5043 reset-mon-config {
5051 aoss2-thermal {
5052 polling-delay-passive = <0>;
5053 polling-delay = <0>;
5054 thermal-sensors = <&tsens2 0>;
5057 thermal-engine-config {
5063 reset-mon-config {
5071 gpuss-0-thermal {
5072 polling-delay-passive = <10>;
5073 polling-delay = <0>;
5074 thermal-sensors = <&tsens2 1>;
5077 thermal-engine-config {
5083 thermal-hal-config {
5089 reset-mon-config {
5095 gpu0_junction_config: junction-config {
5103 gpuss-1-thermal {
5104 polling-delay-passive = <10>;
5105 polling-delay = <0>;
5106 thermal-sensors = <&tsens2 2>;
5109 thermal-engine-config {
5115 thermal-hal-config {
5121 reset-mon-config {
5127 gpu1_junction_config: junction-config {
5135 gpuss-2-thermal {
5136 polling-delay-passive = <10>;
5137 polling-delay = <0>;
5138 thermal-sensors = <&tsens2 3>;
5141 thermal-engine-config {
5147 thermal-hal-config {
5153 reset-mon-config {
5159 gpu2_junction_config: junction-config {
5167 gpuss-3-thermal {
5168 polling-delay-passive = <10>;
5169 polling-delay = <0>;
5170 thermal-sensors = <&tsens2 4>;
5173 thermal-engine-config {
5179 thermal-hal-config {
5185 reset-mon-config {
5191 gpu3_junction_config: junction-config {
5199 gpuss-4-thermal {
5200 polling-delay-passive = <10>;
5201 polling-delay = <0>;
5202 thermal-sensors = <&tsens2 5>;
5205 thermal-engine-config {
5211 thermal-hal-config {
5217 reset-mon-config {
5223 gpu4_junction_config: junction-config {
5231 gpuss-5-thermal {
5232 polling-delay-passive = <10>;
5233 polling-delay = <0>;
5234 thermal-sensors = <&tsens2 6>;
5237 thermal-engine-config {
5243 thermal-hal-config {
5249 reset-mon-config {
5255 gpu5_junction_config: junction-config {
5263 gpuss-6-thermal {
5264 polling-delay-passive = <10>;
5265 polling-delay = <0>;
5266 thermal-sensors = <&tsens2 7>;
5269 thermal-engine-config {
5275 thermal-hal-config {
5281 reset-mon-config {
5287 gpu6_junction_config: junction-config {
5295 gpuss-7-thermal {
5296 polling-delay-passive = <10>;
5297 polling-delay = <0>;
5298 thermal-sensors = <&tsens2 8>;
5301 thermal-engine-config {
5307 thermal-hal-config {
5313 reset-mon-config {
5319 gpu7_junction_config: junction-config {
5329 compatible = "arm,armv8-timer";