Lines Matching +full:1 +full:c25000
137 clocks = <&cpufreq_hw 1>;
140 qcom,freq-domain = <&cpufreq_hw 1>;
156 clocks = <&cpufreq_hw 1>;
159 qcom,freq-domain = <&cpufreq_hw 1>;
175 clocks = <&cpufreq_hw 1>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
278 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
291 #reset-cells = <1>;
505 qcom,client-id = <1>;
554 #qcom,smem-state-cells = <1>;
578 #qcom,smem-state-cells = <1>;
598 qcom,remote-pid = <1>;
602 #qcom,smem-state-cells = <1>;
613 #qcom,smem-state-cells = <1>;
637 #qcom,smem-state-cells = <1>;
657 #clock-cells = <1>;
658 #reset-cells = <1>;
659 #power-domain-cells = <1>;
680 <&ufs_mem_phy_lanes 1>,
738 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
740 #address-cells = <1>;
754 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
756 #address-cells = <1>;
769 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
770 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
772 #address-cells = <1>;
785 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
786 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
788 #address-cells = <1>;
802 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
804 #address-cells = <1>;
818 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
820 #address-cells = <1>;
834 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
836 #address-cells = <1>;
850 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
852 #address-cells = <1>;
868 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
870 #address-cells = <1>;
897 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
899 #address-cells = <1>;
913 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
915 #address-cells = <1>;
964 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
966 #address-cells = <1>;
980 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
982 #address-cells = <1>;
995 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
996 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
998 #address-cells = <1>;
1011 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1012 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1014 #address-cells = <1>;
1028 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1030 #address-cells = <1>;
1044 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1046 #address-cells = <1>;
1075 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1077 #address-cells = <1>;
1091 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1093 #address-cells = <1>;
1107 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1109 #address-cells = <1>;
1123 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1125 #address-cells = <1>;
1139 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1141 #address-cells = <1>;
1155 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1157 #address-cells = <1>;
1171 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1173 #address-cells = <1>;
1200 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1202 #address-cells = <1>;
1216 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1218 #address-cells = <1>;
1267 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1269 #address-cells = <1>;
1283 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1285 #address-cells = <1>;
1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1301 #address-cells = <1>;
1314 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1315 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1317 #address-cells = <1>;
1331 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1333 #address-cells = <1>;
1347 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1349 #address-cells = <1>;
1363 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1365 #address-cells = <1>;
1379 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1381 #address-cells = <1>;
1395 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1397 #address-cells = <1>;
1411 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1413 #address-cells = <1>;
1427 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1429 #address-cells = <1>;
1443 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1445 #address-cells = <1>;
1500 pcie0: pci@1c00000 {
1511 num-lanes = <1>;
1529 #interrupt-cells = <1>;
1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1569 pcie0_phy: phy@1c06000 {
1593 pcie1: pci@1c08000 {
1602 linux,pci-domain = <1>;
1614 #interrupt-cells = <1>;
1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1652 pcie1_phy: phy@1c0e000 {
1676 ufs_mem_hc: ufshc@1d84000 {
1684 #reset-cells = <1>;
1723 ufs_mem_phy: phy@1d87000 {
1740 ufs_mem_phy_lanes: phy@1d87400 {
1746 #clock-cells = <1>;
1751 cryptobam: dma-controller@1dc4000 {
1755 #dma-cells = <1>;
1764 crypto: crypto@1dfa000 {
1777 ipa: ipa@1e40000 {
1792 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1809 <&ipa_smp2p_out 1>;
1816 tcsr_mutex: hwlock@1f40000 {
1819 #hwlock-cells = <1>;
1828 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1864 #address-cells = <1>;
1880 #address-cells = <1>;
1882 #sound-dai-cells = <1>;
1898 #address-cells = <1>;
1900 #sound-dai-cells = <1>;
1907 dai@1 {
1908 reg = <1>;
1934 #address-cells = <1>;
1984 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
2107 #clock-cells = <1>;
2108 #reset-cells = <1>;
2109 #power-domain-cells = <1>;
2163 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2195 qcom,remote-pid = <1>;
2205 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2242 #address-cells = <1>;
2245 compute-cb@1 {
2247 reg = <1>;
2346 #clock-cells = <1>;
2347 #phy-cells = <1>;
2352 #address-cells = <1>;
2362 port@1 {
2363 reg = <1>;
2444 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2483 #address-cells = <1>;
2486 compute-cb@1 {
2488 reg = <1>;
2598 #address-cells = <1>;
2608 port@1 {
2609 reg = <1>;
2692 #interrupt-cells = <1>;
2760 #address-cells = <1>;
2770 port@1 {
2771 reg = <1>;
2822 #address-cells = <1>;
2882 <&mdss_dsi0_phy 1>;
2889 #address-cells = <1>;
2919 #address-cells = <1>;
2929 port@1 {
2930 reg = <1>;
2946 #clock-cells = <1>;
2980 <&mdss_dsi1_phy 1>;
2987 #address-cells = <1>;
3017 #address-cells = <1>;
3027 port@1 {
3028 reg = <1>;
3044 #clock-cells = <1>;
3059 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
3060 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
3070 #clock-cells = <1>;
3071 #reset-cells = <1>;
3072 #power-domain-cells = <1>;
3080 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3082 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
3097 #thermal-sensor-cells = <1>;
3108 #thermal-sensor-cells = <1>;
3135 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3456 #redistributor-regions = <1>;
3465 #address-cells = <1>;
3466 #size-cells = <1>;
3480 frame-number = <1>;
3486 frame@17c25000 {
3528 reg-names = "drv-0", "drv-1", "drv-2";
3540 #clock-cells = <1>;
3547 #power-domain-cells = <1>;
3611 "dcvsh-irq-1",
3617 #freq-domain-cells = <1>;
3618 #clock-cells = <1>;
3627 thermal-sensors = <&tsens0 1>;
4225 thermal-sensors = <&tsens1 1>;