Lines Matching refs:gcc

7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
133 clocks = <&gcc GCC_USB1_AUX_CLK>,
134 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
138 resets = <&gcc GCC_USB1_PHY_BCR>,
139 <&gcc GCC_USB3PHY_1_PHY_BCR>;
150 clocks = <&gcc GCC_USB1_PIPE_CLK>;
161 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
165 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
176 clocks = <&gcc GCC_USB0_AUX_CLK>,
177 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
181 resets = <&gcc GCC_USB0_PHY_BCR>,
182 <&gcc GCC_USB3PHY_0_PHY_BCR>;
193 clocks = <&gcc GCC_USB0_PIPE_CLK>;
204 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
208 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
219 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
220 <&gcc GCC_PCIE0_AHB_CLK>;
222 resets = <&gcc GCC_PCIE0_PHY_BCR>,
223 <&gcc GCC_PCIE0PHY_PHY_BCR>;
235 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
248 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
249 <&gcc GCC_PCIE1_AHB_CLK>;
251 resets = <&gcc GCC_PCIE1_PHY_BCR>,
252 <&gcc GCC_PCIE1PHY_PHY_BCR>;
263 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
275 clocks = <&gcc GCC_MDIO_AHB_CLK>;
291 clocks = <&gcc GCC_PRNG_AHB_CLK>;
310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
321 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
322 <&gcc GCC_CRYPTO_AXI_CLK>,
323 <&gcc GCC_CRYPTO_CLK>;
380 gcc: gcc@1800000 { label
381 compatible = "qcom,gcc-ipq8074";
428 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
429 <&gcc GCC_SDCC1_APPS_CLK>,
432 resets = <&gcc GCC_SDCC1_BCR>;
446 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
456 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
457 <&gcc GCC_BLSP1_AHB_CLK>;
466 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
467 <&gcc GCC_BLSP1_AHB_CLK>;
481 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
482 <&gcc GCC_BLSP1_AHB_CLK>;
495 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
496 <&gcc GCC_BLSP1_AHB_CLK>;
511 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
512 <&gcc GCC_BLSP1_AHB_CLK>;
528 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
529 <&gcc GCC_BLSP1_AHB_CLK>;
543 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
544 <&gcc GCC_BLSP1_AHB_CLK>;
558 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
559 <&gcc GCC_BLSP1_AHB_CLK>;
572 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
573 <&gcc GCC_BLSP1_AHB_CLK>;
585 clocks = <&gcc GCC_QPIC_AHB_CLK>;
597 clocks = <&gcc GCC_QPIC_CLK>,
598 <&gcc GCC_QPIC_AHB_CLK>;
617 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
618 <&gcc GCC_USB0_MASTER_CLK>,
619 <&gcc GCC_USB0_SLEEP_CLK>,
620 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
626 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
627 <&gcc GCC_USB0_MASTER_CLK>,
628 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
633 power-domains = <&gcc USB0_GDSC>;
635 resets = <&gcc GCC_USB0_BCR>;
660 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
661 <&gcc GCC_USB1_MASTER_CLK>,
662 <&gcc GCC_USB1_SLEEP_CLK>,
663 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
669 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
670 <&gcc GCC_USB1_MASTER_CLK>,
671 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
676 power-domains = <&gcc USB1_GDSC>;
678 resets = <&gcc GCC_USB1_BCR>;
831 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
832 <&gcc GCC_PCIE1_AXI_M_CLK>,
833 <&gcc GCC_PCIE1_AXI_S_CLK>,
834 <&gcc GCC_PCIE1_AHB_CLK>,
835 <&gcc GCC_PCIE1_AUX_CLK>;
841 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
842 <&gcc GCC_PCIE1_SLEEP_ARES>,
843 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
844 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
845 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
846 <&gcc GCC_PCIE1_AHB_ARES>,
847 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
893 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
894 <&gcc GCC_PCIE0_AXI_M_CLK>,
895 <&gcc GCC_PCIE0_AXI_S_CLK>,
896 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
897 <&gcc GCC_PCIE0_RCHNG_CLK>;
904 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
905 <&gcc GCC_PCIE0_SLEEP_ARES>,
906 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
907 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
908 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
909 <&gcc GCC_PCIE0_AHB_ARES>,
910 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
911 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;