Lines Matching refs:gcc
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
229 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
233 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
244 clocks = <&gcc GCC_USB0_AUX_CLK>,
245 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
248 resets = <&gcc GCC_USB0_PHY_BCR>,
249 <&gcc GCC_USB3PHY_0_PHY_BCR>;
260 clocks = <&gcc GCC_USB0_PIPE_CLK>;
271 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
275 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
287 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
288 <&gcc GCC_PCIE0_AHB_CLK>;
291 resets = <&gcc GCC_PCIE0_PHY_BCR>,
292 <&gcc GCC_PCIE0PHY_PHY_BCR>;
303 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
315 clocks = <&gcc GCC_MDIO_AHB_CLK>;
330 clocks = <&gcc GCC_PRNG_AHB_CLK>;
338 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
348 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
349 <&gcc GCC_CRYPTO_AXI_CLK>,
350 <&gcc GCC_CRYPTO_CLK>;
385 gcc: gcc@1800000 { label
386 compatible = "qcom,gcc-ipq6018";
411 clocks = <&gcc GCC_USB1_MASTER_CLK>,
412 <&gcc GCC_USB1_SLEEP_CLK>,
413 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
418 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
419 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
422 resets = <&gcc GCC_USB1_BCR>;
444 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
454 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
455 <&gcc GCC_BLSP1_AHB_CLK>;
466 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
467 <&gcc GCC_BLSP1_AHB_CLK>;
480 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
481 <&gcc GCC_BLSP1_AHB_CLK>;
494 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
495 <&gcc GCC_BLSP1_AHB_CLK>;
509 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
510 <&gcc GCC_BLSP1_AHB_CLK>;
522 clocks = <&gcc GCC_QPIC_AHB_CLK>;
534 clocks = <&gcc GCC_QPIC_CLK>,
535 <&gcc GCC_QPIC_AHB_CLK>;
554 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
555 <&gcc GCC_USB0_MASTER_CLK>,
556 <&gcc GCC_USB0_SLEEP_CLK>,
557 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
563 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
564 <&gcc GCC_USB0_MASTER_CLK>,
565 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
570 resets = <&gcc GCC_USB0_BCR>;
711 resets = <&gcc GCC_WCSSAON_RESET>,
712 <&gcc GCC_WCSS_BCR>,
713 <&gcc GCC_WCSS_Q6_BCR>;
719 clocks = <&gcc GCC_PRNG_AHB_CLK>;
776 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
777 <&gcc GCC_PCIE0_AXI_M_CLK>,
778 <&gcc GCC_PCIE0_AXI_S_CLK>,
779 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
780 <&gcc PCIE0_RCHNG_CLK>;
787 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
788 <&gcc GCC_PCIE0_SLEEP_ARES>,
789 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
790 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
791 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
792 <&gcc GCC_PCIE0_AHB_ARES>,
793 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
794 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;