Lines Matching +full:tegra210 +full:- +full:amx
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 compatible = "simple-bus";
23 #address-cells = <2>;
24 #size-cells = <2>;
28 compatible = "nvidia,tegra194-misc";
34 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security", "gpio";
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pinmux 0 0 169>;
93 cbb-noc@2300000 {
94 compatible = "nvidia,tegra194-cbb-noc";
104 compatible = "nvidia,tegra194-axi2apb";
115 compatible = "nvidia,tegra194-pinmux";
119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {
123 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
124 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
134 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
135 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
143 compatible = "nvidia,tegra194-eqos",
144 "nvidia,tegra186-eqos",
145 "snps,dwc-qos-ethernet-4.10";
153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
155 reset-names = "eqos";
158 interconnect-names = "dma-mem", "write";
162 snps,write-requests = <1>;
163 snps,read-requests = <3>;
164 snps,burst-map = <0x7>;
169 gpcdma: dma-controller@2600000 {
170 compatible = "nvidia,tegra194-gpcdma",
171 "nvidia,tegra186-gpcdma";
174 reset-names = "gpcdma";
207 #dma-cells = <1>;
209 dma-coherent;
210 dma-channel-mask = <0xfffffffe>;
215 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,tegra210-aconnect";
219 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
223 #address-cells = <2>;
224 #size-cells = <2>;
228 compatible = "nvidia,tegra194-ahub",
229 "nvidia,tegra186-ahub";
232 clock-names = "ahub";
233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
235 assigned-clock-rates = <81600000>;
238 #address-cells = <2>;
239 #size-cells = <2>;
243 compatible = "nvidia,tegra194-i2s",
244 "nvidia,tegra210-i2s";
248 clock-names = "i2s", "sync_input";
249 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assigned-clock-rates = <1536000>;
252 sound-name-prefix = "I2S1";
257 compatible = "nvidia,tegra194-i2s",
258 "nvidia,tegra210-i2s";
262 clock-names = "i2s", "sync_input";
263 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assigned-clock-rates = <1536000>;
266 sound-name-prefix = "I2S2";
271 compatible = "nvidia,tegra194-i2s",
272 "nvidia,tegra210-i2s";
276 clock-names = "i2s", "sync_input";
277 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assigned-clock-rates = <1536000>;
280 sound-name-prefix = "I2S3";
285 compatible = "nvidia,tegra194-i2s",
286 "nvidia,tegra210-i2s";
290 clock-names = "i2s", "sync_input";
291 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assigned-clock-rates = <1536000>;
294 sound-name-prefix = "I2S4";
299 compatible = "nvidia,tegra194-i2s",
300 "nvidia,tegra210-i2s";
304 clock-names = "i2s", "sync_input";
305 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assigned-clock-rates = <1536000>;
308 sound-name-prefix = "I2S5";
313 compatible = "nvidia,tegra194-i2s",
314 "nvidia,tegra210-i2s";
318 clock-names = "i2s", "sync_input";
319 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assigned-clock-rates = <1536000>;
322 sound-name-prefix = "I2S6";
327 compatible = "nvidia,tegra194-sfc",
328 "nvidia,tegra210-sfc";
330 sound-name-prefix = "SFC1";
335 compatible = "nvidia,tegra194-sfc",
336 "nvidia,tegra210-sfc";
338 sound-name-prefix = "SFC2";
343 compatible = "nvidia,tegra194-sfc",
344 "nvidia,tegra210-sfc";
346 sound-name-prefix = "SFC3";
351 compatible = "nvidia,tegra194-sfc",
352 "nvidia,tegra210-sfc";
354 sound-name-prefix = "SFC4";
358 tegra_amx1: amx@2903000 {
359 compatible = "nvidia,tegra194-amx";
361 sound-name-prefix = "AMX1";
365 tegra_amx2: amx@2903100 {
366 compatible = "nvidia,tegra194-amx";
368 sound-name-prefix = "AMX2";
372 tegra_amx3: amx@2903200 {
373 compatible = "nvidia,tegra194-amx";
375 sound-name-prefix = "AMX3";
379 tegra_amx4: amx@2903300 {
380 compatible = "nvidia,tegra194-amx";
382 sound-name-prefix = "AMX4";
387 compatible = "nvidia,tegra194-adx",
388 "nvidia,tegra210-adx";
390 sound-name-prefix = "ADX1";
395 compatible = "nvidia,tegra194-adx",
396 "nvidia,tegra210-adx";
398 sound-name-prefix = "ADX2";
403 compatible = "nvidia,tegra194-adx",
404 "nvidia,tegra210-adx";
406 sound-name-prefix = "ADX3";
411 compatible = "nvidia,tegra194-adx",
412 "nvidia,tegra210-adx";
414 sound-name-prefix = "ADX4";
419 compatible = "nvidia,tegra194-dmic",
420 "nvidia,tegra210-dmic";
423 clock-names = "dmic";
424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assigned-clock-rates = <3072000>;
427 sound-name-prefix = "DMIC1";
432 compatible = "nvidia,tegra194-dmic",
433 "nvidia,tegra210-dmic";
436 clock-names = "dmic";
437 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assigned-clock-rates = <3072000>;
440 sound-name-prefix = "DMIC2";
445 compatible = "nvidia,tegra194-dmic",
446 "nvidia,tegra210-dmic";
449 clock-names = "dmic";
450 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assigned-clock-rates = <3072000>;
453 sound-name-prefix = "DMIC3";
458 compatible = "nvidia,tegra194-dmic",
459 "nvidia,tegra210-dmic";
462 clock-names = "dmic";
463 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assigned-clock-rates = <3072000>;
466 sound-name-prefix = "DMIC4";
471 compatible = "nvidia,tegra194-dspk",
472 "nvidia,tegra186-dspk";
475 clock-names = "dspk";
476 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assigned-clock-rates = <12288000>;
479 sound-name-prefix = "DSPK1";
484 compatible = "nvidia,tegra194-dspk",
485 "nvidia,tegra186-dspk";
488 clock-names = "dspk";
489 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assigned-clock-rates = <12288000>;
492 sound-name-prefix = "DSPK2";
496 tegra_ope1: processing-engine@2908000 {
497 compatible = "nvidia,tegra194-ope",
498 "nvidia,tegra210-ope";
500 sound-name-prefix = "OPE1";
503 #address-cells = <2>;
504 #size-cells = <2>;
508 compatible = "nvidia,tegra194-peq",
509 "nvidia,tegra210-peq";
513 dynamic-range-compressor@2908200 {
514 compatible = "nvidia,tegra194-mbdrc",
515 "nvidia,tegra210-mbdrc";
521 compatible = "nvidia,tegra194-mvc",
522 "nvidia,tegra210-mvc";
524 sound-name-prefix = "MVC1";
529 compatible = "nvidia,tegra194-mvc",
530 "nvidia,tegra210-mvc";
532 sound-name-prefix = "MVC2";
537 compatible = "nvidia,tegra194-amixer",
538 "nvidia,tegra210-amixer";
540 sound-name-prefix = "MIXER1";
545 compatible = "nvidia,tegra194-admaif",
546 "nvidia,tegra186-admaif";
568 dma-names = "rx1", "tx1",
591 interconnect-names = "dma-mem", "write";
596 compatible = "nvidia,tegra194-asrc",
597 "nvidia,tegra186-asrc";
599 sound-name-prefix = "ASRC1";
604 adma: dma-controller@2930000 {
605 compatible = "nvidia,tegra194-adma",
606 "nvidia,tegra186-adma";
608 interrupt-parent = <&agic>;
641 #dma-cells = <1>;
643 clock-names = "d_audio";
647 agic: interrupt-controller@2a40000 {
648 compatible = "nvidia,tegra194-agic",
649 "nvidia,tegra210-agic";
650 #interrupt-cells = <3>;
651 interrupt-controller;
658 clock-names = "clk";
663 mc: memory-controller@2c00000 {
664 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
683 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
687 #interconnect-cells = <1>;
690 #address-cells = <2>;
691 #size-cells = <2>;
711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
713 emc: external-memory-controller@2c60000 {
714 compatible = "nvidia,tegra194-emc";
719 clock-names = "emc";
721 #interconnect-cells = <0>;
728 compatible = "nvidia,tegra186-timer";
744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
746 reg-shift = <2>;
754 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
756 reg-shift = <2>;
764 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
766 reg-shift = <2>;
774 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
776 reg-shift = <2>;
784 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
786 reg-shift = <2>;
794 compatible = "nvidia,tegra194-i2c";
797 #address-cells = <1>;
798 #size-cells = <0>;
800 clock-names = "div-clk";
802 reset-names = "i2c";
804 dma-names = "rx", "tx";
809 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
811 reg-shift = <2>;
819 compatible = "nvidia,tegra194-i2c";
822 #address-cells = <1>;
823 #size-cells = <0>;
825 clock-names = "div-clk";
827 reset-names = "i2c";
829 dma-names = "rx", "tx";
835 compatible = "nvidia,tegra194-i2c";
838 #address-cells = <1>;
839 #size-cells = <0>;
841 clock-names = "div-clk";
843 reset-names = "i2c";
844 pinctrl-0 = <&state_dpaux1_i2c>;
845 pinctrl-1 = <&state_dpaux1_off>;
846 pinctrl-names = "default", "idle";
848 dma-names = "rx", "tx";
854 compatible = "nvidia,tegra194-i2c";
857 #address-cells = <1>;
858 #size-cells = <0>;
860 clock-names = "div-clk";
862 reset-names = "i2c";
863 pinctrl-0 = <&state_dpaux0_i2c>;
864 pinctrl-1 = <&state_dpaux0_off>;
865 pinctrl-names = "default", "idle";
867 dma-names = "rx", "tx";
873 compatible = "nvidia,tegra194-i2c";
876 #address-cells = <1>;
877 #size-cells = <0>;
879 clock-names = "div-clk";
881 reset-names = "i2c";
882 pinctrl-0 = <&state_dpaux2_i2c>;
883 pinctrl-1 = <&state_dpaux2_off>;
884 pinctrl-names = "default", "idle";
886 dma-names = "rx", "tx";
892 compatible = "nvidia,tegra194-i2c";
895 #address-cells = <1>;
896 #size-cells = <0>;
898 clock-names = "div-clk";
900 reset-names = "i2c";
901 pinctrl-0 = <&state_dpaux3_i2c>;
902 pinctrl-1 = <&state_dpaux3_off>;
903 pinctrl-names = "default", "idle";
905 dma-names = "rx", "tx";
910 compatible = "nvidia,tegra194-qspi";
913 #address-cells = <1>;
914 #size-cells = <0>;
917 clock-names = "qspi", "qspi_out";
923 compatible = "nvidia,tegra194-pwm",
924 "nvidia,tegra186-pwm";
928 reset-names = "pwm";
930 #pwm-cells = <2>;
934 compatible = "nvidia,tegra194-pwm",
935 "nvidia,tegra186-pwm";
939 reset-names = "pwm";
941 #pwm-cells = <2>;
945 compatible = "nvidia,tegra194-pwm",
946 "nvidia,tegra186-pwm";
950 reset-names = "pwm";
952 #pwm-cells = <2>;
956 compatible = "nvidia,tegra194-pwm",
957 "nvidia,tegra186-pwm";
961 reset-names = "pwm";
963 #pwm-cells = <2>;
967 compatible = "nvidia,tegra194-pwm",
968 "nvidia,tegra186-pwm";
972 reset-names = "pwm";
974 #pwm-cells = <2>;
978 compatible = "nvidia,tegra194-pwm",
979 "nvidia,tegra186-pwm";
983 reset-names = "pwm";
985 #pwm-cells = <2>;
989 compatible = "nvidia,tegra194-pwm",
990 "nvidia,tegra186-pwm";
994 reset-names = "pwm";
996 #pwm-cells = <2>;
1000 compatible = "nvidia,tegra194-qspi";
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1007 clock-names = "qspi", "qspi_out";
1013 compatible = "nvidia,tegra194-sdhci";
1018 clock-names = "sdhci", "tmclk";
1019 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1021 assigned-clock-parents =
1025 reset-names = "sdhci";
1028 interconnect-names = "dma-mem", "write";
1030 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1031 pinctrl-0 = <&sdmmc1_3v3>;
1032 pinctrl-1 = <&sdmmc1_1v8>;
1033 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1035 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1037 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1038 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1040 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1041 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1042 nvidia,default-tap = <0x9>;
1043 nvidia,default-trim = <0x5>;
1044 sd-uhs-sdr25;
1045 sd-uhs-sdr50;
1046 sd-uhs-ddr50;
1047 sd-uhs-sdr104;
1052 compatible = "nvidia,tegra194-sdhci";
1057 clock-names = "sdhci", "tmclk";
1058 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1060 assigned-clock-parents =
1064 reset-names = "sdhci";
1067 interconnect-names = "dma-mem", "write";
1069 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1070 pinctrl-0 = <&sdmmc3_3v3>;
1071 pinctrl-1 = <&sdmmc3_1v8>;
1072 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1073 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1074 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1075 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1077 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1078 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1080 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1081 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1082 nvidia,default-tap = <0x9>;
1083 nvidia,default-trim = <0x5>;
1084 sd-uhs-sdr25;
1085 sd-uhs-sdr50;
1086 sd-uhs-ddr50;
1087 sd-uhs-sdr104;
1092 compatible = "nvidia,tegra194-sdhci";
1097 clock-names = "sdhci", "tmclk";
1098 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1100 assigned-clock-parents =
1103 reset-names = "sdhci";
1106 interconnect-names = "dma-mem", "write";
1108 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1109 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1110 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1111 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1113 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1114 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1116 nvidia,default-tap = <0x8>;
1117 nvidia,default-trim = <0x14>;
1118 nvidia,dqs-trim = <40>;
1119 cap-mmc-highspeed;
1120 mmc-ddr-1_8v;
1121 mmc-hs200-1_8v;
1122 mmc-hs400-1_8v;
1123 mmc-hs400-enhanced-strobe;
1124 supports-cqe;
1129 compatible = "nvidia,tegra194-hda";
1135 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1138 reset-names = "hda", "hda2hdmi";
1139 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1142 interconnect-names = "dma-mem", "write";
1148 compatible = "nvidia,tegra194-xusb-padctl";
1151 reg-names = "padctl", "ao";
1155 reset-names = "padctl";
1162 clock-names = "trk";
1165 usb2-0 {
1168 #phy-cells = <0>;
1171 usb2-1 {
1174 #phy-cells = <0>;
1177 usb2-2 {
1180 #phy-cells = <0>;
1183 usb2-3 {
1186 #phy-cells = <0>;
1193 usb3-0 {
1196 #phy-cells = <0>;
1199 usb3-1 {
1202 #phy-cells = <0>;
1205 usb3-2 {
1208 #phy-cells = <0>;
1211 usb3-3 {
1214 #phy-cells = <0>;
1221 usb2-0 {
1225 usb2-1 {
1229 usb2-2 {
1233 usb2-3 {
1237 usb3-0 {
1241 usb3-1 {
1245 usb3-2 {
1249 usb3-3 {
1256 compatible = "nvidia,tegra194-xudc";
1259 reg-names = "base", "fpci";
1265 clock-names = "dev", "ss", "ss_src", "fs_src";
1268 interconnect-names = "dma-mem", "write";
1270 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1272 power-domain-names = "dev", "ss";
1273 nvidia,xusb-padctl = <&xusb_padctl>;
1274 dma-coherent;
1279 compatible = "nvidia,tegra194-xusb";
1282 reg-names = "hcd", "fpci";
1296 clock-names = "xusb_host", "xusb_falcon_src",
1302 interconnect-names = "dma-mem", "write";
1305 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1307 power-domain-names = "xusb_host", "xusb_ss";
1309 nvidia,xusb-padctl = <&xusb_padctl>;
1314 compatible = "nvidia,tegra194-efuse";
1317 clock-names = "fuse";
1320 gic: interrupt-controller@3881000 {
1321 compatible = "arm,gic-400";
1322 #interrupt-cells = <3>;
1323 interrupt-controller;
1330 interrupt-parent = <&gic>;
1334 compatible = "nvidia,tegra194-cec";
1338 clock-names = "cec";
1342 hte_lic: hardware-timestamp@3aa0000 {
1343 compatible = "nvidia,tegra194-gte-lic";
1346 nvidia,int-threshold = <1>;
1348 #timestamp-cells = <1>;
1353 compatible = "nvidia,tegra194-hsp";
1364 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1367 #mbox-cells = <2>;
1371 compatible = "nvidia,tegra194-p2u";
1373 reg-names = "ctl";
1375 #phy-cells = <0>;
1379 compatible = "nvidia,tegra194-p2u";
1381 reg-names = "ctl";
1383 #phy-cells = <0>;
1387 compatible = "nvidia,tegra194-p2u";
1389 reg-names = "ctl";
1391 #phy-cells = <0>;
1395 compatible = "nvidia,tegra194-p2u";
1397 reg-names = "ctl";
1399 #phy-cells = <0>;
1403 compatible = "nvidia,tegra194-p2u";
1405 reg-names = "ctl";
1407 #phy-cells = <0>;
1411 compatible = "nvidia,tegra194-p2u";
1413 reg-names = "ctl";
1415 #phy-cells = <0>;
1419 compatible = "nvidia,tegra194-p2u";
1421 reg-names = "ctl";
1423 #phy-cells = <0>;
1427 compatible = "nvidia,tegra194-p2u";
1429 reg-names = "ctl";
1431 #phy-cells = <0>;
1435 compatible = "nvidia,tegra194-p2u";
1437 reg-names = "ctl";
1439 #phy-cells = <0>;
1443 compatible = "nvidia,tegra194-p2u";
1445 reg-names = "ctl";
1447 #phy-cells = <0>;
1451 compatible = "nvidia,tegra194-p2u";
1453 reg-names = "ctl";
1455 #phy-cells = <0>;
1459 compatible = "nvidia,tegra194-p2u";
1461 reg-names = "ctl";
1463 #phy-cells = <0>;
1467 compatible = "nvidia,tegra194-p2u";
1469 reg-names = "ctl";
1471 #phy-cells = <0>;
1475 compatible = "nvidia,tegra194-p2u";
1477 reg-names = "ctl";
1479 #phy-cells = <0>;
1483 compatible = "nvidia,tegra194-p2u";
1485 reg-names = "ctl";
1487 #phy-cells = <0>;
1491 compatible = "nvidia,tegra194-p2u";
1493 reg-names = "ctl";
1495 #phy-cells = <0>;
1499 compatible = "nvidia,tegra194-p2u";
1501 reg-names = "ctl";
1503 #phy-cells = <0>;
1507 compatible = "nvidia,tegra194-p2u";
1509 reg-names = "ctl";
1511 #phy-cells = <0>;
1515 compatible = "nvidia,tegra194-p2u";
1517 reg-names = "ctl";
1519 #phy-cells = <0>;
1523 compatible = "nvidia,tegra194-p2u";
1525 reg-names = "ctl";
1527 #phy-cells = <0>;
1530 sce-noc@b600000 {
1531 compatible = "nvidia,tegra194-sce-noc";
1540 rce-noc@be00000 {
1541 compatible = "nvidia,tegra194-rce-noc";
1551 compatible = "nvidia,tegra194-hsp";
1561 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1562 #mbox-cells = <2>;
1565 hte_aon: hardware-timestamp@c1e0000 {
1566 compatible = "nvidia,tegra194-gte-aon";
1569 nvidia,int-threshold = <1>;
1571 #timestamp-cells = <1>;
1576 compatible = "nvidia,tegra194-i2c";
1579 #address-cells = <1>;
1580 #size-cells = <0>;
1582 clock-names = "div-clk";
1584 reset-names = "i2c";
1586 dma-names = "rx", "tx";
1591 compatible = "nvidia,tegra194-i2c";
1594 #address-cells = <1>;
1595 #size-cells = <0>;
1597 clock-names = "div-clk";
1599 reset-names = "i2c";
1601 dma-names = "rx", "tx";
1606 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1608 reg-shift = <2>;
1616 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1618 reg-shift = <2>;
1626 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1628 interrupt-parent = <&pmc>;
1631 clock-names = "rtc";
1636 compatible = "nvidia,tegra194-gpio-aon";
1637 reg-names = "security", "gpio";
1644 gpio-controller;
1645 #gpio-cells = <2>;
1646 interrupt-controller;
1647 #interrupt-cells = <2>;
1648 gpio-ranges = <&pinmux_aon 0 0 30>;
1652 compatible = "nvidia,tegra194-pinmux-aon";
1659 compatible = "nvidia,tegra194-pwm",
1660 "nvidia,tegra186-pwm";
1664 reset-names = "pwm";
1666 #pwm-cells = <2>;
1670 compatible = "nvidia,tegra194-pmc";
1676 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1678 #interrupt-cells = <2>;
1679 interrupt-controller;
1681 sdmmc1_1v8: sdmmc1-1v8 {
1682 pins = "sdmmc1-hv";
1683 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1686 sdmmc1_3v3: sdmmc1-3v3 {
1687 pins = "sdmmc1-hv";
1688 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1691 sdmmc3_1v8: sdmmc3-1v8 {
1692 pins = "sdmmc3-hv";
1693 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1696 sdmmc3_3v3: sdmmc3-3v3 {
1697 pins = "sdmmc3-hv";
1698 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1702 aon-noc@c600000 {
1703 compatible = "nvidia,tegra194-aon-noc";
1711 bpmp-noc@d600000 {
1712 compatible = "nvidia,tegra194-bpmp-noc";
1722 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1789 stream-match-mask = <0x7f80>;
1790 #global-interrupts = <1>;
1791 #iommu-cells = <1>;
1793 nvidia,memory-controller = <&mc>;
1798 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1867 stream-match-mask = <0x7f80>;
1868 #global-interrupts = <2>;
1869 #iommu-cells = <1>;
1871 nvidia,memory-controller = <&mc>;
1876 compatible = "nvidia,tegra194-host1x";
1879 reg-names = "hypervisor", "vm";
1882 interrupt-names = "syncpt", "host1x";
1884 clock-names = "host1x";
1886 reset-names = "host1x";
1888 #address-cells = <2>;
1889 #size-cells = <2>;
1893 interconnect-names = "dma-mem";
1895 dma-coherent;
1898 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1908 compatible = "nvidia,tegra194-nvdec";
1911 clock-names = "nvdec";
1913 reset-names = "nvdec";
1915 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1919 interconnect-names = "dma-mem", "read-1", "write";
1921 dma-coherent;
1923 nvidia,host1x-class = <0xf5>;
1926 display-hub@15200000 {
1927 compatible = "nvidia,tegra194-display";
1936 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1940 clock-names = "disp", "hub";
1943 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1945 #address-cells = <2>;
1946 #size-cells = <2>;
1950 compatible = "nvidia,tegra194-dc";
1954 clock-names = "dc";
1956 reset-names = "dc";
1958 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1961 interconnect-names = "dma-mem", "read-1";
1968 compatible = "nvidia,tegra194-dc";
1972 clock-names = "dc";
1974 reset-names = "dc";
1976 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1979 interconnect-names = "dma-mem", "read-1";
1986 compatible = "nvidia,tegra194-dc";
1990 clock-names = "dc";
1992 reset-names = "dc";
1994 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1997 interconnect-names = "dma-mem", "read-1";
2004 compatible = "nvidia,tegra194-dc";
2008 clock-names = "dc";
2010 reset-names = "dc";
2012 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2015 interconnect-names = "dma-mem", "read-1";
2023 compatible = "nvidia,tegra194-vic";
2027 clock-names = "vic";
2029 reset-names = "vic";
2031 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2034 interconnect-names = "dma-mem", "write";
2036 dma-coherent;
2040 compatible = "nvidia,tegra194-nvjpg";
2043 clock-names = "nvjpg";
2045 reset-names = "nvjpg";
2047 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2050 interconnect-names = "dma-mem", "write";
2052 dma-coherent;
2056 compatible = "nvidia,tegra194-nvdec";
2059 clock-names = "nvdec";
2061 reset-names = "nvdec";
2063 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2067 interconnect-names = "dma-mem", "read-1", "write";
2069 dma-coherent;
2071 nvidia,host1x-class = <0xf0>;
2075 compatible = "nvidia,tegra194-nvenc";
2078 clock-names = "nvenc";
2080 reset-names = "nvenc";
2082 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2086 interconnect-names = "dma-mem", "read-1", "write";
2088 dma-coherent;
2090 nvidia,host1x-class = <0x21>;
2094 compatible = "nvidia,tegra194-dpaux";
2099 clock-names = "dpaux", "parent";
2101 reset-names = "dpaux";
2104 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2106 state_dpaux0_aux: pinmux-aux {
2107 groups = "dpaux-io";
2111 state_dpaux0_i2c: pinmux-i2c {
2112 groups = "dpaux-io";
2116 state_dpaux0_off: pinmux-off {
2117 groups = "dpaux-io";
2121 i2c-bus {
2122 #address-cells = <1>;
2123 #size-cells = <0>;
2128 compatible = "nvidia,tegra194-dpaux";
2133 clock-names = "dpaux", "parent";
2135 reset-names = "dpaux";
2138 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2140 state_dpaux1_aux: pinmux-aux {
2141 groups = "dpaux-io";
2145 state_dpaux1_i2c: pinmux-i2c {
2146 groups = "dpaux-io";
2150 state_dpaux1_off: pinmux-off {
2151 groups = "dpaux-io";
2155 i2c-bus {
2156 #address-cells = <1>;
2157 #size-cells = <0>;
2162 compatible = "nvidia,tegra194-dpaux";
2167 clock-names = "dpaux", "parent";
2169 reset-names = "dpaux";
2172 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2174 state_dpaux2_aux: pinmux-aux {
2175 groups = "dpaux-io";
2179 state_dpaux2_i2c: pinmux-i2c {
2180 groups = "dpaux-io";
2184 state_dpaux2_off: pinmux-off {
2185 groups = "dpaux-io";
2189 i2c-bus {
2190 #address-cells = <1>;
2191 #size-cells = <0>;
2196 compatible = "nvidia,tegra194-dpaux";
2201 clock-names = "dpaux", "parent";
2203 reset-names = "dpaux";
2206 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2208 state_dpaux3_aux: pinmux-aux {
2209 groups = "dpaux-io";
2213 state_dpaux3_i2c: pinmux-i2c {
2214 groups = "dpaux-io";
2218 state_dpaux3_off: pinmux-off {
2219 groups = "dpaux-io";
2223 i2c-bus {
2224 #address-cells = <1>;
2225 #size-cells = <0>;
2230 compatible = "nvidia,tegra194-nvenc";
2233 clock-names = "nvenc";
2235 reset-names = "nvenc";
2237 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2241 interconnect-names = "dma-mem", "read-1", "write";
2243 dma-coherent;
2245 nvidia,host1x-class = <0x22>;
2249 compatible = "nvidia,tegra194-sor";
2258 clock-names = "sor", "out", "parent", "dp", "safe",
2261 reset-names = "sor";
2262 pinctrl-0 = <&state_dpaux0_aux>;
2263 pinctrl-1 = <&state_dpaux0_i2c>;
2264 pinctrl-2 = <&state_dpaux0_off>;
2265 pinctrl-names = "aux", "i2c", "off";
2268 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2273 compatible = "nvidia,tegra194-sor";
2282 clock-names = "sor", "out", "parent", "dp", "safe",
2285 reset-names = "sor";
2286 pinctrl-0 = <&state_dpaux1_aux>;
2287 pinctrl-1 = <&state_dpaux1_i2c>;
2288 pinctrl-2 = <&state_dpaux1_off>;
2289 pinctrl-names = "aux", "i2c", "off";
2292 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2297 compatible = "nvidia,tegra194-sor";
2306 clock-names = "sor", "out", "parent", "dp", "safe",
2309 reset-names = "sor";
2310 pinctrl-0 = <&state_dpaux2_aux>;
2311 pinctrl-1 = <&state_dpaux2_i2c>;
2312 pinctrl-2 = <&state_dpaux2_off>;
2313 pinctrl-names = "aux", "i2c", "off";
2316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2321 compatible = "nvidia,tegra194-sor";
2330 clock-names = "sor", "out", "parent", "dp", "safe",
2333 reset-names = "sor";
2334 pinctrl-0 = <&state_dpaux3_aux>;
2335 pinctrl-1 = <&state_dpaux3_i2c>;
2336 pinctrl-2 = <&state_dpaux3_off>;
2337 pinctrl-names = "aux", "i2c", "off";
2340 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2346 compatible = "nvidia,tegra194-pcie";
2347 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2352 reg-names = "appl", "config", "atu_dma", "dbi";
2356 #address-cells = <3>;
2357 #size-cells = <2>;
2359 num-lanes = <1>;
2360 linux,pci-domain = <1>;
2363 clock-names = "core";
2367 reset-names = "apb", "core";
2371 interrupt-names = "intr", "msi";
2373 #interrupt-cells = <1>;
2374 interrupt-map-mask = <0 0 0 0>;
2375 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2379 nvidia,aspm-cmrt-us = <60>;
2380 nvidia,aspm-pwr-on-t-us = <20>;
2381 nvidia,aspm-l0s-entrance-latency-us = <3>;
2383 bus-range = <0x0 0xff>;
2386 …00000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2391 interconnect-names = "dma-mem", "write";
2392 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2393 iommu-map-mask = <0x0>;
2394 dma-coherent;
2398 compatible = "nvidia,tegra194-pcie";
2399 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2404 reg-names = "appl", "config", "atu_dma", "dbi";
2408 #address-cells = <3>;
2409 #size-cells = <2>;
2411 num-lanes = <1>;
2412 linux,pci-domain = <2>;
2415 clock-names = "core";
2419 reset-names = "apb", "core";
2423 interrupt-names = "intr", "msi";
2425 #interrupt-cells = <1>;
2426 interrupt-map-mask = <0 0 0 0>;
2427 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2431 nvidia,aspm-cmrt-us = <60>;
2432 nvidia,aspm-pwr-on-t-us = <20>;
2433 nvidia,aspm-l0s-entrance-latency-us = <3>;
2435 bus-range = <0x0 0xff>;
2438 …00000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2443 interconnect-names = "dma-mem", "write";
2444 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2445 iommu-map-mask = <0x0>;
2446 dma-coherent;
2450 compatible = "nvidia,tegra194-pcie";
2451 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2456 reg-names = "appl", "config", "atu_dma", "dbi";
2460 #address-cells = <3>;
2461 #size-cells = <2>;
2463 num-lanes = <1>;
2464 linux,pci-domain = <3>;
2467 clock-names = "core";
2471 reset-names = "apb", "core";
2475 interrupt-names = "intr", "msi";
2477 #interrupt-cells = <1>;
2478 interrupt-map-mask = <0 0 0 0>;
2479 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2483 nvidia,aspm-cmrt-us = <60>;
2484 nvidia,aspm-pwr-on-t-us = <20>;
2485 nvidia,aspm-l0s-entrance-latency-us = <3>;
2487 bus-range = <0x0 0xff>;
2490 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
2495 interconnect-names = "dma-mem", "write";
2496 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2497 iommu-map-mask = <0x0>;
2498 dma-coherent;
2502 compatible = "nvidia,tegra194-pcie";
2503 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2508 reg-names = "appl", "config", "atu_dma", "dbi";
2512 #address-cells = <3>;
2513 #size-cells = <2>;
2515 num-lanes = <4>;
2516 linux,pci-domain = <4>;
2519 clock-names = "core";
2523 reset-names = "apb", "core";
2527 interrupt-names = "intr", "msi";
2529 #interrupt-cells = <1>;
2530 interrupt-map-mask = <0 0 0 0>;
2531 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2535 nvidia,aspm-cmrt-us = <60>;
2536 nvidia,aspm-pwr-on-t-us = <20>;
2537 nvidia,aspm-l0s-entrance-latency-us = <3>;
2539 bus-range = <0x0 0xff>;
2542 …000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2547 interconnect-names = "dma-mem", "write";
2548 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2549 iommu-map-mask = <0x0>;
2550 dma-coherent;
2553 pcie-ep@14160000 {
2554 compatible = "nvidia,tegra194-pcie-ep";
2555 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2560 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2564 num-lanes = <4>;
2565 num-ib-windows = <2>;
2566 num-ob-windows = <8>;
2569 clock-names = "core";
2573 reset-names = "apb", "core";
2576 interrupt-names = "intr";
2580 nvidia,aspm-cmrt-us = <60>;
2581 nvidia,aspm-pwr-on-t-us = <20>;
2582 nvidia,aspm-l0s-entrance-latency-us = <3>;
2586 interconnect-names = "dma-mem", "write";
2587 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2588 iommu-map-mask = <0x0>;
2589 dma-coherent;
2593 compatible = "nvidia,tegra194-pcie";
2594 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2599 reg-names = "appl", "config", "atu_dma", "dbi";
2603 #address-cells = <3>;
2604 #size-cells = <2>;
2606 num-lanes = <8>;
2607 linux,pci-domain = <0>;
2610 clock-names = "core";
2614 reset-names = "apb", "core";
2618 interrupt-names = "intr", "msi";
2620 #interrupt-cells = <1>;
2621 interrupt-map-mask = <0 0 0 0>;
2622 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2626 nvidia,aspm-cmrt-us = <60>;
2627 nvidia,aspm-pwr-on-t-us = <20>;
2628 nvidia,aspm-l0s-entrance-latency-us = <3>;
2630 bus-range = <0x0 0xff>;
2633 …000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2638 interconnect-names = "dma-mem", "write";
2639 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2640 iommu-map-mask = <0x0>;
2641 dma-coherent;
2644 pcie-ep@14180000 {
2645 compatible = "nvidia,tegra194-pcie-ep";
2646 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2651 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2655 num-lanes = <8>;
2656 num-ib-windows = <2>;
2657 num-ob-windows = <8>;
2660 clock-names = "core";
2664 reset-names = "apb", "core";
2667 interrupt-names = "intr";
2671 nvidia,aspm-cmrt-us = <60>;
2672 nvidia,aspm-pwr-on-t-us = <20>;
2673 nvidia,aspm-l0s-entrance-latency-us = <3>;
2677 interconnect-names = "dma-mem", "write";
2678 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2679 iommu-map-mask = <0x0>;
2680 dma-coherent;
2684 compatible = "nvidia,tegra194-pcie";
2685 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2690 reg-names = "appl", "config", "atu_dma", "dbi";
2694 #address-cells = <3>;
2695 #size-cells = <2>;
2697 num-lanes = <8>;
2698 linux,pci-domain = <5>;
2700 pinctrl-names = "default";
2701 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>;
2704 clock-names = "core";
2708 reset-names = "apb", "core";
2712 interrupt-names = "intr", "msi";
2716 #interrupt-cells = <1>;
2717 interrupt-map-mask = <0 0 0 0>;
2718 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2720 nvidia,aspm-cmrt-us = <60>;
2721 nvidia,aspm-pwr-on-t-us = <20>;
2722 nvidia,aspm-l0s-entrance-latency-us = <3>;
2724 bus-range = <0x0 0xff>;
2727 …000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2732 interconnect-names = "dma-mem", "write";
2733 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2734 iommu-map-mask = <0x0>;
2735 dma-coherent;
2738 pcie-ep@141a0000 {
2739 compatible = "nvidia,tegra194-pcie-ep";
2740 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2745 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2749 num-lanes = <8>;
2750 num-ib-windows = <2>;
2751 num-ob-windows = <8>;
2753 pinctrl-names = "default";
2754 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>;
2757 clock-names = "core";
2761 reset-names = "apb", "core";
2764 interrupt-names = "intr";
2768 nvidia,aspm-cmrt-us = <60>;
2769 nvidia,aspm-pwr-on-t-us = <20>;
2770 nvidia,aspm-l0s-entrance-latency-us = <3>;
2774 interconnect-names = "dma-mem", "write";
2775 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2776 iommu-map-mask = <0x0>;
2777 dma-coherent;
2786 interrupt-names = "stall", "nonstall";
2790 clock-names = "gpu", "pwr", "fuse";
2792 reset-names = "gpu";
2793 dma-coherent;
2795 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2808 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2809 "read-1", "read-1-hp", "write-1",
2810 "read-2", "read-2-hp", "write-2",
2811 "read-3", "read-3-hp", "write-3";
2816 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2819 #address-cells = <1>;
2820 #size-cells = <1>;
2823 no-memory-wc;
2827 label = "cpu-bpmp-tx";
2833 label = "cpu-bpmp-rx";
2839 compatible = "nvidia,tegra186-bpmp";
2843 #clock-cells = <1>;
2844 #reset-cells = <1>;
2845 #power-domain-cells = <1>;
2850 interconnect-names = "read", "write", "dma-mem", "dma-write";
2854 compatible = "nvidia,tegra186-bpmp-i2c";
2855 nvidia,bpmp-bus-id = <5>;
2856 #address-cells = <1>;
2857 #size-cells = <0>;
2861 compatible = "nvidia,tegra186-bpmp-thermal";
2862 #thermal-sensor-cells = <1>;
2867 compatible = "nvidia,tegra194-ccplex";
2869 #address-cells = <1>;
2870 #size-cells = <0>;
2873 compatible = "nvidia,tegra194-carmel";
2876 enable-method = "psci";
2877 i-cache-size = <131072>;
2878 i-cache-line-size = <64>;
2879 i-cache-sets = <512>;
2880 d-cache-size = <65536>;
2881 d-cache-line-size = <64>;
2882 d-cache-sets = <256>;
2883 next-level-cache = <&l2c_0>;
2887 compatible = "nvidia,tegra194-carmel";
2890 enable-method = "psci";
2891 i-cache-size = <131072>;
2892 i-cache-line-size = <64>;
2893 i-cache-sets = <512>;
2894 d-cache-size = <65536>;
2895 d-cache-line-size = <64>;
2896 d-cache-sets = <256>;
2897 next-level-cache = <&l2c_0>;
2901 compatible = "nvidia,tegra194-carmel";
2904 enable-method = "psci";
2905 i-cache-size = <131072>;
2906 i-cache-line-size = <64>;
2907 i-cache-sets = <512>;
2908 d-cache-size = <65536>;
2909 d-cache-line-size = <64>;
2910 d-cache-sets = <256>;
2911 next-level-cache = <&l2c_1>;
2915 compatible = "nvidia,tegra194-carmel";
2918 enable-method = "psci";
2919 i-cache-size = <131072>;
2920 i-cache-line-size = <64>;
2921 i-cache-sets = <512>;
2922 d-cache-size = <65536>;
2923 d-cache-line-size = <64>;
2924 d-cache-sets = <256>;
2925 next-level-cache = <&l2c_1>;
2929 compatible = "nvidia,tegra194-carmel";
2932 enable-method = "psci";
2933 i-cache-size = <131072>;
2934 i-cache-line-size = <64>;
2935 i-cache-sets = <512>;
2936 d-cache-size = <65536>;
2937 d-cache-line-size = <64>;
2938 d-cache-sets = <256>;
2939 next-level-cache = <&l2c_2>;
2943 compatible = "nvidia,tegra194-carmel";
2946 enable-method = "psci";
2947 i-cache-size = <131072>;
2948 i-cache-line-size = <64>;
2949 i-cache-sets = <512>;
2950 d-cache-size = <65536>;
2951 d-cache-line-size = <64>;
2952 d-cache-sets = <256>;
2953 next-level-cache = <&l2c_2>;
2957 compatible = "nvidia,tegra194-carmel";
2960 enable-method = "psci";
2961 i-cache-size = <131072>;
2962 i-cache-line-size = <64>;
2963 i-cache-sets = <512>;
2964 d-cache-size = <65536>;
2965 d-cache-line-size = <64>;
2966 d-cache-sets = <256>;
2967 next-level-cache = <&l2c_3>;
2971 compatible = "nvidia,tegra194-carmel";
2974 enable-method = "psci";
2975 i-cache-size = <131072>;
2976 i-cache-line-size = <64>;
2977 i-cache-sets = <512>;
2978 d-cache-size = <65536>;
2979 d-cache-line-size = <64>;
2980 d-cache-sets = <256>;
2981 next-level-cache = <&l2c_3>;
2984 cpu-map {
3026 l2c_0: l2-cache0 {
3028 cache-unified;
3029 cache-size = <2097152>;
3030 cache-line-size = <64>;
3031 cache-sets = <2048>;
3032 cache-level = <2>;
3033 next-level-cache = <&l3c>;
3036 l2c_1: l2-cache1 {
3038 cache-unified;
3039 cache-size = <2097152>;
3040 cache-line-size = <64>;
3041 cache-sets = <2048>;
3042 cache-level = <2>;
3043 next-level-cache = <&l3c>;
3046 l2c_2: l2-cache2 {
3048 cache-unified;
3049 cache-size = <2097152>;
3050 cache-line-size = <64>;
3051 cache-sets = <2048>;
3052 cache-level = <2>;
3053 next-level-cache = <&l3c>;
3056 l2c_3: l2-cache3 {
3058 cache-unified;
3059 cache-size = <2097152>;
3060 cache-line-size = <64>;
3061 cache-sets = <2048>;
3062 cache-level = <2>;
3063 next-level-cache = <&l3c>;
3066 l3c: l3-cache {
3068 cache-unified;
3069 cache-size = <4194304>;
3070 cache-line-size = <64>;
3071 cache-level = <3>;
3072 cache-sets = <4096>;
3077 compatible = "nvidia,carmel-pmu";
3086 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3091 compatible = "arm,psci-1.0";
3097 compatible = "nvidia,tegra194-tcu";
3100 mbox-names = "rx", "tx";
3108 clock-names = "pll_a", "plla_out0";
3109 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3112 assigned-clock-parents = <0>,
3120 assigned-clock-rates = <258000000>;
3123 thermal-zones {
3124 cpu-thermal {
3125 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3129 gpu-thermal {
3130 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3134 aux-thermal {
3135 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3139 pllx-thermal {
3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3144 ao-thermal {
3145 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3149 tj-thermal {
3150 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3156 compatible = "arm,armv8-timer";
3165 interrupt-parent = <&gic>;
3166 always-on;