Lines Matching +full:tegra20 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "nvidia,tegra186-misc";
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
62 reset-names = "eqos";
65 interconnect-names = "dma-mem", "write";
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
80 reset-names = "gpcdma";
113 #dma-cells = <1>;
115 dma-coherent;
116 dma-channel-mask = <0xfffffffe>;
121 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210-aconnect";
125 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <1>;
128 #size-cells = <1>;
133 compatible = "nvidia,tegra186-ahub";
136 clock-names = "ahub";
137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
139 assigned-clock-rates = <81600000>;
140 #address-cells = <1>;
141 #size-cells = <1>;
145 tegra_i2s1: i2s@2901000 {
146 compatible = "nvidia,tegra186-i2s",
147 "nvidia,tegra210-i2s";
151 clock-names = "i2s", "sync_input";
152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
154 assigned-clock-rates = <1536000>;
155 sound-name-prefix = "I2S1";
159 tegra_i2s2: i2s@2901100 {
160 compatible = "nvidia,tegra186-i2s",
161 "nvidia,tegra210-i2s";
165 clock-names = "i2s", "sync_input";
166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
168 assigned-clock-rates = <1536000>;
169 sound-name-prefix = "I2S2";
173 tegra_i2s3: i2s@2901200 {
174 compatible = "nvidia,tegra186-i2s",
175 "nvidia,tegra210-i2s";
179 clock-names = "i2s", "sync_input";
180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
182 assigned-clock-rates = <1536000>;
183 sound-name-prefix = "I2S3";
187 tegra_i2s4: i2s@2901300 {
188 compatible = "nvidia,tegra186-i2s",
189 "nvidia,tegra210-i2s";
193 clock-names = "i2s", "sync_input";
194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
196 assigned-clock-rates = <1536000>;
197 sound-name-prefix = "I2S4";
201 tegra_i2s5: i2s@2901400 {
202 compatible = "nvidia,tegra186-i2s",
203 "nvidia,tegra210-i2s";
207 clock-names = "i2s", "sync_input";
208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
210 assigned-clock-rates = <1536000>;
211 sound-name-prefix = "I2S5";
215 tegra_i2s6: i2s@2901500 {
216 compatible = "nvidia,tegra186-i2s",
217 "nvidia,tegra210-i2s";
221 clock-names = "i2s", "sync_input";
222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
224 assigned-clock-rates = <1536000>;
225 sound-name-prefix = "I2S6";
230 compatible = "nvidia,tegra186-sfc",
231 "nvidia,tegra210-sfc";
233 sound-name-prefix = "SFC1";
238 compatible = "nvidia,tegra186-sfc",
239 "nvidia,tegra210-sfc";
241 sound-name-prefix = "SFC2";
246 compatible = "nvidia,tegra186-sfc",
247 "nvidia,tegra210-sfc";
249 sound-name-prefix = "SFC3";
254 compatible = "nvidia,tegra186-sfc",
255 "nvidia,tegra210-sfc";
257 sound-name-prefix = "SFC4";
262 compatible = "nvidia,tegra186-amx",
263 "nvidia,tegra210-amx";
265 sound-name-prefix = "AMX1";
270 compatible = "nvidia,tegra186-amx",
271 "nvidia,tegra210-amx";
273 sound-name-prefix = "AMX2";
278 compatible = "nvidia,tegra186-amx",
279 "nvidia,tegra210-amx";
281 sound-name-prefix = "AMX3";
286 compatible = "nvidia,tegra186-amx",
287 "nvidia,tegra210-amx";
289 sound-name-prefix = "AMX4";
294 compatible = "nvidia,tegra186-adx",
295 "nvidia,tegra210-adx";
297 sound-name-prefix = "ADX1";
302 compatible = "nvidia,tegra186-adx",
303 "nvidia,tegra210-adx";
305 sound-name-prefix = "ADX2";
310 compatible = "nvidia,tegra186-adx",
311 "nvidia,tegra210-adx";
313 sound-name-prefix = "ADX3";
318 compatible = "nvidia,tegra186-adx",
319 "nvidia,tegra210-adx";
321 sound-name-prefix = "ADX4";
326 compatible = "nvidia,tegra210-dmic";
329 clock-names = "dmic";
330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
332 assigned-clock-rates = <3072000>;
333 sound-name-prefix = "DMIC1";
338 compatible = "nvidia,tegra210-dmic";
341 clock-names = "dmic";
342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
344 assigned-clock-rates = <3072000>;
345 sound-name-prefix = "DMIC2";
350 compatible = "nvidia,tegra210-dmic";
353 clock-names = "dmic";
354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
356 assigned-clock-rates = <3072000>;
357 sound-name-prefix = "DMIC3";
362 compatible = "nvidia,tegra210-dmic";
365 clock-names = "dmic";
366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
368 assigned-clock-rates = <3072000>;
369 sound-name-prefix = "DMIC4";
374 compatible = "nvidia,tegra186-dspk";
377 clock-names = "dspk";
378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
380 assigned-clock-rates = <12288000>;
381 sound-name-prefix = "DSPK1";
386 compatible = "nvidia,tegra186-dspk";
389 clock-names = "dspk";
390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
392 assigned-clock-rates = <12288000>;
393 sound-name-prefix = "DSPK2";
397 tegra_ope1: processing-engine@2908000 {
398 compatible = "nvidia,tegra186-ope",
399 "nvidia,tegra210-ope";
401 #address-cells = <1>;
402 #size-cells = <1>;
404 sound-name-prefix = "OPE1";
408 compatible = "nvidia,tegra186-peq",
409 "nvidia,tegra210-peq";
413 dynamic-range-compressor@2908200 {
414 compatible = "nvidia,tegra186-mbdrc",
415 "nvidia,tegra210-mbdrc";
421 compatible = "nvidia,tegra186-mvc",
422 "nvidia,tegra210-mvc";
424 sound-name-prefix = "MVC1";
429 compatible = "nvidia,tegra186-mvc",
430 "nvidia,tegra210-mvc";
432 sound-name-prefix = "MVC2";
437 compatible = "nvidia,tegra186-amixer",
438 "nvidia,tegra210-amixer";
440 sound-name-prefix = "MIXER1";
445 compatible = "nvidia,tegra186-admaif";
467 dma-names = "rx1", "tx1",
491 compatible = "nvidia,tegra186-asrc";
493 sound-name-prefix = "ASRC1";
498 adma: dma-controller@2930000 {
499 compatible = "nvidia,tegra186-adma";
501 interrupt-parent = <&agic>;
534 #dma-cells = <1>;
536 clock-names = "d_audio";
540 agic: interrupt-controller@2a40000 {
541 compatible = "nvidia,tegra186-agic",
542 "nvidia,tegra210-agic";
543 #interrupt-cells = <3>;
544 interrupt-controller;
550 clock-names = "clk";
555 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
567 #interconnect-cells = <1>;
568 #address-cells = <2>;
569 #size-cells = <2>;
577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
579 emc: external-memory-controller@2c60000 {
580 compatible = "nvidia,tegra186-emc";
584 clock-names = "emc";
586 #interconnect-cells = <0>;
593 compatible = "nvidia,tegra186-timer";
609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
611 reg-shift = <2>;
619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
621 reg-shift = <2>;
629 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
631 reg-shift = <2>;
639 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
641 reg-shift = <2>;
649 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
651 reg-shift = <2>;
659 compatible = "nvidia,tegra186-i2c";
662 #address-cells = <1>;
663 #size-cells = <0>;
665 clock-names = "div-clk";
667 reset-names = "i2c";
669 dma-names = "rx", "tx";
674 compatible = "nvidia,tegra186-i2c";
677 #address-cells = <1>;
678 #size-cells = <0>;
680 clock-names = "div-clk";
682 reset-names = "i2c";
684 dma-names = "rx", "tx";
690 compatible = "nvidia,tegra186-i2c";
693 #address-cells = <1>;
694 #size-cells = <0>;
696 clock-names = "div-clk";
698 reset-names = "i2c";
699 pinctrl-names = "default", "idle";
700 pinctrl-0 = <&state_dpaux1_i2c>;
701 pinctrl-1 = <&state_dpaux1_off>;
703 dma-names = "rx", "tx";
709 compatible = "nvidia,tegra186-i2c";
712 #address-cells = <1>;
713 #size-cells = <0>;
715 clock-names = "div-clk";
717 reset-names = "i2c";
723 compatible = "nvidia,tegra186-i2c";
726 #address-cells = <1>;
727 #size-cells = <0>;
729 clock-names = "div-clk";
731 reset-names = "i2c";
732 pinctrl-names = "default", "idle";
733 pinctrl-0 = <&state_dpaux_i2c>;
734 pinctrl-1 = <&state_dpaux_off>;
736 dma-names = "rx", "tx";
741 compatible = "nvidia,tegra186-i2c";
744 #address-cells = <1>;
745 #size-cells = <0>;
747 clock-names = "div-clk";
749 reset-names = "i2c";
751 dma-names = "rx", "tx";
756 compatible = "nvidia,tegra186-i2c";
759 #address-cells = <1>;
760 #size-cells = <0>;
762 clock-names = "div-clk";
764 reset-names = "i2c";
766 dma-names = "rx", "tx";
771 compatible = "nvidia,tegra186-pwm";
775 reset-names = "pwm";
777 #pwm-cells = <2>;
781 compatible = "nvidia,tegra186-pwm";
785 reset-names = "pwm";
787 #pwm-cells = <2>;
791 compatible = "nvidia,tegra186-pwm";
795 reset-names = "pwm";
797 #pwm-cells = <2>;
801 compatible = "nvidia,tegra186-pwm";
805 reset-names = "pwm";
807 #pwm-cells = <2>;
811 compatible = "nvidia,tegra186-pwm";
815 reset-names = "pwm";
817 #pwm-cells = <2>;
821 compatible = "nvidia,tegra186-pwm";
825 reset-names = "pwm";
827 #pwm-cells = <2>;
831 compatible = "nvidia,tegra186-pwm";
835 reset-names = "pwm";
837 #pwm-cells = <2>;
841 compatible = "nvidia,tegra186-sdhci";
846 clock-names = "sdhci", "tmclk";
848 reset-names = "sdhci";
851 interconnect-names = "dma-mem", "write";
853 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
854 pinctrl-0 = <&sdmmc1_3v3>;
855 pinctrl-1 = <&sdmmc1_1v8>;
856 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
857 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
858 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
859 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
860 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
861 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
862 nvidia,default-tap = <0x5>;
863 nvidia,default-trim = <0xb>;
864 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
866 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
871 compatible = "nvidia,tegra186-sdhci";
876 clock-names = "sdhci", "tmclk";
878 reset-names = "sdhci";
881 interconnect-names = "dma-mem", "write";
883 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
884 pinctrl-0 = <&sdmmc2_3v3>;
885 pinctrl-1 = <&sdmmc2_1v8>;
886 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
887 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
888 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
889 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
890 nvidia,default-tap = <0x5>;
891 nvidia,default-trim = <0xb>;
896 compatible = "nvidia,tegra186-sdhci";
901 clock-names = "sdhci", "tmclk";
903 reset-names = "sdhci";
906 interconnect-names = "dma-mem", "write";
908 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
909 pinctrl-0 = <&sdmmc3_3v3>;
910 pinctrl-1 = <&sdmmc3_1v8>;
911 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
912 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
913 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
914 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
915 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
916 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
917 nvidia,default-tap = <0x5>;
918 nvidia,default-trim = <0xb>;
923 compatible = "nvidia,tegra186-sdhci";
928 clock-names = "sdhci", "tmclk";
929 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
931 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
933 reset-names = "sdhci";
936 interconnect-names = "dma-mem", "write";
938 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
939 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
940 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
941 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
942 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
943 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
944 nvidia,default-tap = <0x9>;
945 nvidia,default-trim = <0x5>;
946 nvidia,dqs-trim = <63>;
947 mmc-hs400-1_8v;
948 supports-cqe;
953 compatible = "nvidia,tegra186-ahci";
959 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
962 interconnect-names = "dma-mem", "write";
967 clock-names = "sata", "sata-oob";
968 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
970 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
972 assigned-clock-rates = <102000000>,
976 reset-names = "sata", "sata-cold";
981 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
987 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
991 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
992 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
995 interconnect-names = "dma-mem", "write";
1001 compatible = "nvidia,tegra186-xusb-padctl";
1004 reg-names = "padctl", "ao";
1008 reset-names = "padctl";
1015 clock-names = "trk";
1019 usb2-0 {
1021 #phy-cells = <0>;
1024 usb2-1 {
1026 #phy-cells = <0>;
1029 usb2-2 {
1031 #phy-cells = <0>;
1038 clock-names = "trk";
1042 hsic-0 {
1044 #phy-cells = <0>;
1053 usb3-0 {
1055 #phy-cells = <0>;
1058 usb3-1 {
1060 #phy-cells = <0>;
1063 usb3-2 {
1065 #phy-cells = <0>;
1072 usb2-0 {
1076 usb2-1 {
1080 usb2-2 {
1084 hsic-0 {
1088 usb3-0 {
1092 usb3-1 {
1096 usb3-2 {
1103 compatible = "nvidia,tegra186-xusb";
1106 reg-names = "hcd", "fpci";
1118 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1121 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1123 power-domain-names = "xusb_host", "xusb_ss";
1126 interconnect-names = "dma-mem", "write";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1132 nvidia,xusb-padctl = <&padctl>;
1136 compatible = "nvidia,tegra186-xudc";
1139 reg-names = "base", "fpci";
1145 clock-names = "dev", "ss", "ss_src", "fs_src";
1148 interconnect-names = "dma-mem", "write";
1150 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1152 power-domain-names = "dev", "ss";
1153 nvidia,xusb-padctl = <&padctl>;
1158 compatible = "nvidia,tegra186-efuse";
1161 clock-names = "fuse";
1164 gic: interrupt-controller@3881000 {
1165 compatible = "arm,gic-400";
1166 #interrupt-cells = <3>;
1167 interrupt-controller;
1174 interrupt-parent = <&gic>;
1178 compatible = "nvidia,tegra186-cec";
1182 clock-names = "cec";
1187 compatible = "nvidia,tegra186-hsp";
1190 interrupt-names = "doorbell";
1191 #mbox-cells = <2>;
1196 compatible = "nvidia,tegra186-i2c";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1202 clock-names = "div-clk";
1204 reset-names = "i2c";
1206 dma-names = "rx", "tx";
1211 compatible = "nvidia,tegra186-i2c";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1217 clock-names = "div-clk";
1219 reset-names = "i2c";
1221 dma-names = "rx", "tx";
1226 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1228 reg-shift = <2>;
1236 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1238 reg-shift = <2>;
1246 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1248 interrupt-parent = <&pmc>;
1251 clock-names = "rtc";
1256 compatible = "nvidia,tegra186-gpio-aon";
1257 reg-names = "security", "gpio";
1261 gpio-controller;
1262 #gpio-cells = <2>;
1263 interrupt-controller;
1264 #interrupt-cells = <2>;
1268 compatible = "nvidia,tegra186-pwm";
1272 reset-names = "pwm";
1274 #pwm-cells = <2>;
1278 compatible = "nvidia,tegra186-pmc";
1283 reg-names = "pmc", "wake", "aotag", "scratch";
1285 #interrupt-cells = <2>;
1286 interrupt-controller;
1288 sdmmc1_1v8: sdmmc1-1v8 {
1289 pins = "sdmmc1-hv";
1290 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1293 sdmmc1_3v3: sdmmc1-3v3 {
1294 pins = "sdmmc1-hv";
1295 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1298 sdmmc2_1v8: sdmmc2-1v8 {
1299 pins = "sdmmc2-hv";
1300 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1303 sdmmc2_3v3: sdmmc2-3v3 {
1304 pins = "sdmmc2-hv";
1305 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1308 sdmmc3_1v8: sdmmc3-1v8 {
1309 pins = "sdmmc3-hv";
1310 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1313 sdmmc3_3v3: sdmmc3-3v3 {
1314 pins = "sdmmc3-hv";
1315 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1320 compatible = "nvidia,tegra186-ccplex-cluster";
1327 compatible = "nvidia,tegra186-pcie";
1328 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1333 reg-names = "pads", "afi", "cs";
1337 interrupt-names = "intr", "msi";
1339 #interrupt-cells = <1>;
1340 interrupt-map-mask = <0 0 0 0>;
1341 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1343 bus-range = <0x00 0xff>;
1344 #address-cells = <3>;
1345 #size-cells = <2>;
1351 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1357 clock-names = "pex", "afi", "pll_e";
1362 reset-names = "pex", "afi", "pcie_x";
1366 interconnect-names = "dma-mem", "write";
1369 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1370 iommu-map-mask = <0x0>;
1376 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1380 #address-cells = <3>;
1381 #size-cells = <2>;
1384 nvidia,num-lanes = <2>;
1389 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1393 #address-cells = <3>;
1394 #size-cells = <2>;
1397 nvidia,num-lanes = <1>;
1402 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1406 #address-cells = <3>;
1407 #size-cells = <2>;
1410 nvidia,num-lanes = <1>;
1415 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1482 stream-match-mask = <0x7f80>;
1483 #global-interrupts = <1>;
1484 #iommu-cells = <1>;
1486 nvidia,memory-controller = <&mc>;
1490 compatible = "nvidia,tegra186-host1x";
1493 reg-names = "hypervisor", "vm";
1496 interrupt-names = "syncpt", "host1x";
1498 clock-names = "host1x";
1500 reset-names = "host1x";
1502 #address-cells = <1>;
1503 #size-cells = <1>;
1508 interconnect-names = "dma-mem";
1513 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1523 compatible = "nvidia,tegra186-dpaux";
1528 clock-names = "dpaux", "parent";
1530 reset-names = "dpaux";
1533 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1535 state_dpaux1_aux: pinmux-aux {
1536 groups = "dpaux-io";
1540 state_dpaux1_i2c: pinmux-i2c {
1541 groups = "dpaux-io";
1545 state_dpaux1_off: pinmux-off {
1546 groups = "dpaux-io";
1550 i2c-bus {
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1556 display-hub@15200000 {
1557 compatible = "nvidia,tegra186-display";
1566 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1571 clock-names = "disp", "dsc", "hub";
1574 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1576 #address-cells = <1>;
1577 #size-cells = <1>;
1582 compatible = "nvidia,tegra186-dc";
1586 clock-names = "dc";
1588 reset-names = "dc";
1590 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1593 interconnect-names = "dma-mem", "read-1";
1601 compatible = "nvidia,tegra186-dc";
1605 clock-names = "dc";
1607 reset-names = "dc";
1609 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1612 interconnect-names = "dma-mem", "read-1";
1620 compatible = "nvidia,tegra186-dc";
1624 clock-names = "dc";
1626 reset-names = "dc";
1628 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1631 interconnect-names = "dma-mem", "read-1";
1640 compatible = "nvidia,tegra186-dsi";
1646 clock-names = "dsi", "lp", "parent";
1648 reset-names = "dsi";
1651 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1655 compatible = "nvidia,tegra186-vic";
1659 clock-names = "vic";
1661 reset-names = "vic";
1663 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1666 interconnect-names = "dma-mem", "write";
1671 compatible = "nvidia,tegra186-nvjpg";
1674 clock-names = "nvjpg";
1676 reset-names = "nvjpg";
1678 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1681 interconnect-names = "dma-mem", "write";
1686 compatible = "nvidia,tegra186-dsi";
1692 clock-names = "dsi", "lp", "parent";
1694 reset-names = "dsi";
1697 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1701 compatible = "nvidia,tegra186-nvdec";
1704 clock-names = "nvdec";
1706 reset-names = "nvdec";
1708 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1712 interconnect-names = "dma-mem", "read-1", "write";
1717 compatible = "nvidia,tegra186-nvenc";
1720 clock-names = "nvenc";
1722 reset-names = "nvenc";
1724 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1727 interconnect-names = "dma-mem", "write";
1732 compatible = "nvidia,tegra186-sor";
1741 clock-names = "sor", "out", "parent", "dp", "safe",
1744 reset-names = "sor";
1745 pinctrl-0 = <&state_dpaux_aux>;
1746 pinctrl-1 = <&state_dpaux_i2c>;
1747 pinctrl-2 = <&state_dpaux_off>;
1748 pinctrl-names = "aux", "i2c", "off";
1751 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1756 compatible = "nvidia,tegra186-sor";
1765 clock-names = "sor", "out", "parent", "dp", "safe",
1768 reset-names = "sor";
1769 pinctrl-0 = <&state_dpaux1_aux>;
1770 pinctrl-1 = <&state_dpaux1_i2c>;
1771 pinctrl-2 = <&state_dpaux1_off>;
1772 pinctrl-names = "aux", "i2c", "off";
1775 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1780 compatible = "nvidia,tegra186-dpaux";
1785 clock-names = "dpaux", "parent";
1787 reset-names = "dpaux";
1790 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1792 state_dpaux_aux: pinmux-aux {
1793 groups = "dpaux-io";
1797 state_dpaux_i2c: pinmux-i2c {
1798 groups = "dpaux-io";
1802 state_dpaux_off: pinmux-off {
1803 groups = "dpaux-io";
1807 i2c-bus {
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1814 compatible = "nvidia,tegra186-dsi-padctl";
1817 reset-names = "dsi";
1822 compatible = "nvidia,tegra186-dsi";
1828 clock-names = "dsi", "lp", "parent";
1830 reset-names = "dsi";
1833 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1837 compatible = "nvidia,tegra186-dsi";
1843 clock-names = "dsi", "lp", "parent";
1845 reset-names = "dsi";
1848 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1858 interrupt-names = "stall", "nonstall";
1862 clock-names = "gpu", "pwr";
1864 reset-names = "gpu";
1867 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1872 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1876 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1878 #address-cells = <1>;
1879 #size-cells = <1>;
1881 no-memory-wc;
1885 label = "cpu-bpmp-tx";
1891 label = "cpu-bpmp-rx";
1897 compatible = "nvidia,tegra186-bpmp";
1902 interconnect-names = "read", "write", "dma-mem", "dma-write";
1907 #clock-cells = <1>;
1908 #reset-cells = <1>;
1909 #power-domain-cells = <1>;
1912 compatible = "nvidia,tegra186-bpmp-i2c";
1913 nvidia,bpmp-bus-id = <5>;
1914 #address-cells = <1>;
1915 #size-cells = <0>;
1920 compatible = "nvidia,tegra186-bpmp-thermal";
1921 #thermal-sensor-cells = <1>;
1926 #address-cells = <1>;
1927 #size-cells = <0>;
1930 compatible = "nvidia,tegra186-denver";
1932 i-cache-size = <0x20000>;
1933 i-cache-line-size = <64>;
1934 i-cache-sets = <512>;
1935 d-cache-size = <0x10000>;
1936 d-cache-line-size = <64>;
1937 d-cache-sets = <256>;
1938 next-level-cache = <&L2_DENVER>;
1943 compatible = "nvidia,tegra186-denver";
1945 i-cache-size = <0x20000>;
1946 i-cache-line-size = <64>;
1947 i-cache-sets = <512>;
1948 d-cache-size = <0x10000>;
1949 d-cache-line-size = <64>;
1950 d-cache-sets = <256>;
1951 next-level-cache = <&L2_DENVER>;
1956 compatible = "arm,cortex-a57";
1958 i-cache-size = <0xC000>;
1959 i-cache-line-size = <64>;
1960 i-cache-sets = <256>;
1961 d-cache-size = <0x8000>;
1962 d-cache-line-size = <64>;
1963 d-cache-sets = <256>;
1964 next-level-cache = <&L2_A57>;
1969 compatible = "arm,cortex-a57";
1971 i-cache-size = <0xC000>;
1972 i-cache-line-size = <64>;
1973 i-cache-sets = <256>;
1974 d-cache-size = <0x8000>;
1975 d-cache-line-size = <64>;
1976 d-cache-sets = <256>;
1977 next-level-cache = <&L2_A57>;
1982 compatible = "arm,cortex-a57";
1984 i-cache-size = <0xC000>;
1985 i-cache-line-size = <64>;
1986 i-cache-sets = <256>;
1987 d-cache-size = <0x8000>;
1988 d-cache-line-size = <64>;
1989 d-cache-sets = <256>;
1990 next-level-cache = <&L2_A57>;
1995 compatible = "arm,cortex-a57";
1997 i-cache-size = <0xC000>;
1998 i-cache-line-size = <64>;
1999 i-cache-sets = <256>;
2000 d-cache-size = <0x8000>;
2001 d-cache-line-size = <64>;
2002 d-cache-sets = <256>;
2003 next-level-cache = <&L2_A57>;
2007 L2_DENVER: l2-cache0 {
2009 cache-unified;
2010 cache-level = <2>;
2011 cache-size = <0x200000>;
2012 cache-line-size = <64>;
2013 cache-sets = <2048>;
2016 L2_A57: l2-cache1 {
2018 cache-unified;
2019 cache-level = <2>;
2020 cache-size = <0x200000>;
2021 cache-line-size = <64>;
2022 cache-sets = <2048>;
2026 pmu-a57 {
2027 compatible = "arm,cortex-a57-pmu";
2032 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2035 pmu-denver {
2036 compatible = "nvidia,denver-pmu";
2039 interrupt-affinity = <&denver_0 &denver_1>;
2047 clock-names = "pll_a", "plla_out0";
2048 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2051 assigned-clock-parents = <0>,
2059 assigned-clock-rates = <258000000>;
2064 thermal-zones {
2065 /* Cortex-A57 cluster */
2066 cpu-thermal {
2067 polling-delay = <0>;
2068 polling-delay-passive = <1000>;
2070 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2080 cooling-maps {
2085 aux-thermal {
2086 polling-delay = <0>;
2087 polling-delay-passive = <1000>;
2089 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2099 cooling-maps {
2103 gpu-thermal {
2104 polling-delay = <0>;
2105 polling-delay-passive = <1000>;
2107 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2117 cooling-maps {
2121 pll-thermal {
2122 polling-delay = <0>;
2123 polling-delay-passive = <1000>;
2125 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2135 cooling-maps {
2139 ao-thermal {
2140 polling-delay = <0>;
2141 polling-delay-passive = <1000>;
2143 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2153 cooling-maps {
2159 compatible = "arm,armv8-timer";
2168 interrupt-parent = <&gic>;
2169 always-on;