Lines Matching +full:mt6577 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
630 "vdosys0-2", "vdosys0-3",
631 "vdosys0-4", "vdosys0-5";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 #power-domain-cells = <1>;
637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
642 clock-names = "vppsys1", "vppsys1-0",
643 "vppsys1-1";
645 #power-domain-cells = <0>;
648 power-domain@MT8195_POWER_DOMAIN_WPESYS {
654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
655 "wepsys-3";
657 #power-domain-cells = <0>;
660 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
663 clock-names = "vdec0-0";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 #power-domain-cells = <0>;
669 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
672 clock-names = "vdec1-0";
674 #power-domain-cells = <0>;
677 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
680 clock-names = "vdec2-0";
682 #power-domain-cells = <0>;
686 power-domain@MT8195_POWER_DOMAIN_VENC {
689 clock-names = "venc0-larb";
691 #address-cells = <1>;
692 #size-cells = <0>;
693 #power-domain-cells = <0>;
695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
698 clock-names = "venc1-larb";
700 #power-domain-cells = <0>;
704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
710 clock-names = "vdosys1", "vdosys1-0",
711 "vdosys1-1", "vdosys1-2";
713 #address-cells = <1>;
714 #size-cells = <0>;
715 #power-domain-cells = <1>;
717 power-domain@MT8195_POWER_DOMAIN_DP_TX {
720 #power-domain-cells = <0>;
723 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
726 #power-domain-cells = <0>;
729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
732 clock-names = "hdmi_tx";
733 #power-domain-cells = <0>;
737 power-domain@MT8195_POWER_DOMAIN_IMG {
741 clock-names = "img-0", "img-1";
743 #address-cells = <1>;
744 #size-cells = <0>;
745 #power-domain-cells = <1>;
747 power-domain@MT8195_POWER_DOMAIN_DIP {
749 #power-domain-cells = <0>;
752 power-domain@MT8195_POWER_DOMAIN_IPE {
757 clock-names = "ipe", "ipe-0", "ipe-1";
759 #power-domain-cells = <0>;
763 power-domain@MT8195_POWER_DOMAIN_CAM {
770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
771 "cam-4";
773 #address-cells = <1>;
774 #size-cells = <0>;
775 #power-domain-cells = <1>;
777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
779 #power-domain-cells = <0>;
782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
784 #power-domain-cells = <0>;
787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
789 #power-domain-cells = <0>;
795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
798 #power-domain-cells = <0>;
801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
804 #power-domain-cells = <0>;
807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
809 #power-domain-cells = <0>;
812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
814 #power-domain-cells = <0>;
817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
821 clock-names = "csi_rx_top", "csi_rx_top1";
822 #power-domain-cells = <0>;
825 power-domain@MT8195_POWER_DOMAIN_ETHER {
828 clock-names = "ether";
829 #power-domain-cells = <0>;
832 power-domain@MT8195_POWER_DOMAIN_ADSP {
836 clock-names = "adsp", "adsp1";
837 #address-cells = <1>;
838 #size-cells = <0>;
840 #power-domain-cells = <1>;
842 power-domain@MT8195_POWER_DOMAIN_AUDIO {
848 clock-names = "audio", "audio1", "audio2",
851 #power-domain-cells = <0>;
858 compatible = "mediatek,mt8195-wdt";
859 mediatek,disable-extrst;
861 #reset-cells = <1>;
865 compatible = "mediatek,mt8195-apmixedsys", "syscon";
867 #clock-cells = <1>;
871 compatible = "mediatek,mt8195-timer",
872 "mediatek,mt6765-timer";
879 compatible = "mediatek,mt8195-pwrap", "syscon";
881 reg-names = "pwrap";
885 clock-names = "spi", "wrap";
886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
891 compatible = "mediatek,mt8195-spmi";
894 reg-names = "pmif", "spmimst";
898 clock-names = "pmif_sys_ck",
901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
905 iommu_infra: infra-iommu@10315000 {
906 compatible = "mediatek,mt8195-iommu-infra";
913 #iommu-cells = <1>;
917 compatible = "mediatek,mt8195-gce";
920 #mbox-cells = <2>;
925 compatible = "mediatek,mt8195-gce";
928 #mbox-cells = <2>;
933 compatible = "mediatek,mt8195-scp";
937 reg-names = "sram", "cfg", "l1tcm";
942 scp_adsp: clock-controller@10720000 {
943 compatible = "mediatek,mt8195-scp_adsp";
945 #clock-cells = <1>;
949 compatible = "mediatek,mt8195-dsp";
952 reg-names = "cfg", "sram";
959 clock-names = "adsp_sel",
965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
966 mbox-names = "rx", "tx";
972 compatible = "mediatek,mt8195-adsp-mbox";
973 #mbox-cells = <0>;
979 compatible = "mediatek,mt8195-adsp-mbox";
980 #mbox-cells = <0>;
985 afe: mt8195-afe-pcm@10890000 {
986 compatible = "mediatek,mt8195-audio";
989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
992 reset-names = "audiosys";
1012 clock-names = "clk26m",
1035 compatible = "mediatek,mt8195-uart",
1036 "mediatek,mt6577-uart";
1040 clock-names = "baud", "bus";
1045 compatible = "mediatek,mt8195-uart",
1046 "mediatek,mt6577-uart";
1050 clock-names = "baud", "bus";
1055 compatible = "mediatek,mt8195-uart",
1056 "mediatek,mt6577-uart";
1060 clock-names = "baud", "bus";
1065 compatible = "mediatek,mt8195-uart",
1066 "mediatek,mt6577-uart";
1070 clock-names = "baud", "bus";
1075 compatible = "mediatek,mt8195-uart",
1076 "mediatek,mt6577-uart";
1080 clock-names = "baud", "bus";
1085 compatible = "mediatek,mt8195-uart",
1086 "mediatek,mt6577-uart";
1090 clock-names = "baud", "bus";
1095 compatible = "mediatek,mt8195-auxadc",
1096 "mediatek,mt8173-auxadc";
1099 clock-names = "main";
1100 #io-channel-cells = <1>;
1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1107 #clock-cells = <1>;
1111 compatible = "mediatek,mt8195-spi",
1112 "mediatek,mt6765-spi";
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1120 clock-names = "parent-clk", "sel-clk", "spi-clk";
1124 lvts_ap: thermal-sensor@1100b000 {
1125 compatible = "mediatek,mt8195-lvts-ap";
1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1132 #thermal-sensor-cells = <1>;
1136 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1139 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1140 #pwm-cells = <2>;
1143 clock-names = "main", "mm";
1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1151 #pwm-cells = <2>;
1154 clock-names = "main", "mm";
1159 compatible = "mediatek,mt8195-spi",
1160 "mediatek,mt6765-spi";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1168 clock-names = "parent-clk", "sel-clk", "spi-clk";
1173 compatible = "mediatek,mt8195-spi",
1174 "mediatek,mt6765-spi";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1182 clock-names = "parent-clk", "sel-clk", "spi-clk";
1187 compatible = "mediatek,mt8195-spi",
1188 "mediatek,mt6765-spi";
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1196 clock-names = "parent-clk", "sel-clk", "spi-clk";
1201 compatible = "mediatek,mt8195-spi",
1202 "mediatek,mt6765-spi";
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1210 clock-names = "parent-clk", "sel-clk", "spi-clk";
1215 compatible = "mediatek,mt8195-spi",
1216 "mediatek,mt6765-spi";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1224 clock-names = "parent-clk", "sel-clk", "spi-clk";
1229 compatible = "mediatek,mt8195-spi-slave";
1233 clock-names = "spi";
1234 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1235 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1240 compatible = "mediatek,mt8195-spi-slave";
1244 clock-names = "spi";
1245 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1246 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1251 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1254 interrupt-names = "macirq";
1255 clock-names = "axi",
1267 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1270 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1273 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1275 snps,axi-config = <&stmmac_axi_setup>;
1276 snps,mtl-rx-config = <&mtl_rx_setup>;
1277 snps,mtl-tx-config = <&mtl_tx_setup>;
1280 snps,clk-csr = <0>;
1284 compatible = "snps,dwmac-mdio";
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1289 stmmac_axi_setup: stmmac-axi-config {
1295 mtl_rx_setup: rx-queues-config {
1296 snps,rx-queues-to-use = <4>;
1297 snps,rx-sched-sp;
1299 snps,dcb-algorithm;
1300 snps,map-to-dma-channel = <0x0>;
1303 snps,dcb-algorithm;
1304 snps,map-to-dma-channel = <0x0>;
1307 snps,dcb-algorithm;
1308 snps,map-to-dma-channel = <0x0>;
1311 snps,dcb-algorithm;
1312 snps,map-to-dma-channel = <0x0>;
1316 mtl_tx_setup: tx-queues-config {
1317 snps,tx-queues-to-use = <4>;
1318 snps,tx-sched-wrr;
1321 snps,dcb-algorithm;
1326 snps,dcb-algorithm;
1331 snps,dcb-algorithm;
1336 snps,dcb-algorithm;
1343 compatible = "mediatek,mt8195-xhci",
1344 "mediatek,mtk-xhci";
1347 reg-names = "mac", "ippc";
1351 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1353 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1360 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1362 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1363 wakeup-source;
1368 compatible = "mediatek,mt8195-mmc",
1369 "mediatek,mt8183-mmc";
1376 clock-names = "source", "hclk", "source_cg";
1381 compatible = "mediatek,mt8195-mmc",
1382 "mediatek,mt8183-mmc";
1389 clock-names = "source", "hclk", "source_cg";
1390 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1391 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1396 compatible = "mediatek,mt8195-mmc",
1397 "mediatek,mt8183-mmc";
1404 clock-names = "source", "hclk", "source_cg";
1405 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1406 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1410 lvts_mcu: thermal-sensor@11278000 {
1411 compatible = "mediatek,mt8195-lvts-mcu";
1416 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1417 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1418 #thermal-sensor-cells = <1>;
1422 compatible = "mediatek,mt8195-xhci",
1423 "mediatek,mtk-xhci";
1426 reg-names = "mac", "ippc";
1429 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1431 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1438 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1440 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1441 wakeup-source;
1446 compatible = "mediatek,mt8195-xhci",
1447 "mediatek,mtk-xhci";
1450 reg-names = "mac", "ippc";
1453 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1455 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1462 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1464 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1465 wakeup-source;
1470 compatible = "mediatek,mt8195-xhci",
1471 "mediatek,mtk-xhci";
1474 reg-names = "mac", "ippc";
1477 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1479 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1486 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1488 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1489 wakeup-source;
1494 compatible = "mediatek,mt8195-pcie",
1495 "mediatek,mt8192-pcie";
1497 #address-cells = <3>;
1498 #size-cells = <2>;
1500 reg-names = "pcie-mac";
1502 bus-range = <0x00 0xff>;
1508 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1509 iommu-map-mask = <0x0>;
1517 clock-names = "pl_250m", "tl_26m", "tl_96m",
1519 assigned-clocks = <&topckgen CLK_TOP_TL>;
1520 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1523 phy-names = "pcie-phy";
1525 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1528 reset-names = "mac";
1530 #interrupt-cells = <1>;
1531 interrupt-map-mask = <0 0 0 7>;
1532 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1538 pcie_intc0: interrupt-controller {
1539 interrupt-controller;
1540 #address-cells = <0>;
1541 #interrupt-cells = <1>;
1546 compatible = "mediatek,mt8195-pcie",
1547 "mediatek,mt8192-pcie";
1549 #address-cells = <3>;
1550 #size-cells = <2>;
1552 reg-names = "pcie-mac";
1554 bus-range = <0x00 0xff>;
1560 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1561 iommu-map-mask = <0x0>;
1570 clock-names = "pl_250m", "tl_26m", "tl_96m",
1572 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1573 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1576 phy-names = "pcie-phy";
1577 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1579 #interrupt-cells = <1>;
1580 interrupt-map-mask = <0 0 0 7>;
1581 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1587 pcie_intc1: interrupt-controller {
1588 interrupt-controller;
1589 #address-cells = <0>;
1590 #interrupt-cells = <1>;
1595 compatible = "mediatek,mt8195-nor",
1596 "mediatek,mt8173-nor";
1602 clock-names = "spi", "sf", "axi";
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1609 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1611 #address-cells = <1>;
1612 #size-cells = <1>;
1613 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1617 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1621 u3_intr_p0: usb3-intr@185 {
1625 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1629 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1633 comb_intr_p1: usb3-intr@187 {
1637 u2_intr_p0: usb2-intr-p0@188,1 {
1641 u2_intr_p1: usb2-intr-p1@188,2 {
1645 u2_intr_p2: usb2-intr-p2@189,1 {
1649 u2_intr_p3: usb2-intr-p3@189,2 {
1653 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1657 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1661 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1665 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1669 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1673 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1677 pciephy_glb_intr: pciephy-glb-intr@193 {
1681 dp_calibration: dp-data@1ac {
1684 lvts_efuse_data1: lvts1-calib@1bc {
1687 lvts_efuse_data2: lvts2-calib@1d0 {
1692 u3phy2: t-phy@11c40000 {
1693 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1694 #address-cells = <1>;
1695 #size-cells = <1>;
1699 u2port2: usb-phy@0 {
1702 clock-names = "ref";
1703 #phy-cells = <1>;
1707 u3phy3: t-phy@11c50000 {
1708 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1709 #address-cells = <1>;
1710 #size-cells = <1>;
1714 u2port3: usb-phy@0 {
1717 clock-names = "ref";
1718 #phy-cells = <1>;
1722 i2c5: i2c@11d00000 {
1723 compatible = "mediatek,mt8195-i2c",
1724 "mediatek,mt8192-i2c";
1728 clock-div = <1>;
1731 clock-names = "main", "dma";
1732 #address-cells = <1>;
1733 #size-cells = <0>;
1737 i2c6: i2c@11d01000 {
1738 compatible = "mediatek,mt8195-i2c",
1739 "mediatek,mt8192-i2c";
1743 clock-div = <1>;
1746 clock-names = "main", "dma";
1747 #address-cells = <1>;
1748 #size-cells = <0>;
1752 i2c7: i2c@11d02000 {
1753 compatible = "mediatek,mt8195-i2c",
1754 "mediatek,mt8192-i2c";
1758 clock-div = <1>;
1761 clock-names = "main", "dma";
1762 #address-cells = <1>;
1763 #size-cells = <0>;
1767 imp_iic_wrap_s: clock-controller@11d03000 {
1768 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1770 #clock-cells = <1>;
1773 i2c0: i2c@11e00000 {
1774 compatible = "mediatek,mt8195-i2c",
1775 "mediatek,mt8192-i2c";
1779 clock-div = <1>;
1782 clock-names = "main", "dma";
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1788 i2c1: i2c@11e01000 {
1789 compatible = "mediatek,mt8195-i2c",
1790 "mediatek,mt8192-i2c";
1794 clock-div = <1>;
1797 clock-names = "main", "dma";
1798 #address-cells = <1>;
1799 #size-cells = <0>;
1803 i2c2: i2c@11e02000 {
1804 compatible = "mediatek,mt8195-i2c",
1805 "mediatek,mt8192-i2c";
1809 clock-div = <1>;
1812 clock-names = "main", "dma";
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1818 i2c3: i2c@11e03000 {
1819 compatible = "mediatek,mt8195-i2c",
1820 "mediatek,mt8192-i2c";
1824 clock-div = <1>;
1827 clock-names = "main", "dma";
1828 #address-cells = <1>;
1829 #size-cells = <0>;
1833 i2c4: i2c@11e04000 {
1834 compatible = "mediatek,mt8195-i2c",
1835 "mediatek,mt8192-i2c";
1839 clock-div = <1>;
1842 clock-names = "main", "dma";
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1848 imp_iic_wrap_w: clock-controller@11e05000 {
1849 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1851 #clock-cells = <1>;
1854 u3phy1: t-phy@11e30000 {
1855 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1856 #address-cells = <1>;
1857 #size-cells = <1>;
1859 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1862 u2port1: usb-phy@0 {
1866 clock-names = "ref", "da_ref";
1867 #phy-cells = <1>;
1870 u3port1: usb-phy@700 {
1874 clock-names = "ref", "da_ref";
1875 nvmem-cells = <&comb_intr_p1>,
1878 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1879 #phy-cells = <1>;
1883 u3phy0: t-phy@11e40000 {
1884 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1885 #address-cells = <1>;
1886 #size-cells = <1>;
1890 u2port0: usb-phy@0 {
1894 clock-names = "ref", "da_ref";
1895 #phy-cells = <1>;
1898 u3port0: usb-phy@700 {
1902 clock-names = "ref", "da_ref";
1903 nvmem-cells = <&u3_intr_p0>,
1906 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1907 #phy-cells = <1>;
1912 compatible = "mediatek,mt8195-pcie-phy";
1914 reg-names = "sif";
1915 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1919 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1923 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1924 #phy-cells = <0>;
1928 ufsphy: ufs-phy@11fa0000 {
1929 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1932 clock-names = "unipro", "mp";
1933 #phy-cells = <0>;
1938 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1939 "arm,mali-valhall-jm";
1946 interrupt-names = "job", "mmu", "gpu";
1947 operating-points-v2 = <&gpu_opp_table>;
1948 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1953 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1957 mfgcfg: clock-controller@13fbf000 {
1958 compatible = "mediatek,mt8195-mfgcfg";
1960 #clock-cells = <1>;
1964 compatible = "mediatek,mt8195-vppsys0", "syscon";
1966 #clock-cells = <1>;
1967 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
1971 compatible = "mediatek,mt8195-vpp-mutex";
1974 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
1976 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1980 compatible = "mediatek,mt8195-smi-sub-common";
1985 clock-names = "apb", "smi", "gals0";
1987 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1991 compatible = "mediatek,mt8195-smi-sub-common";
1996 clock-names = "apb", "smi", "gals0";
1998 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2002 compatible = "mediatek,mt8195-smi-common-vpp";
2008 clock-names = "apb", "smi", "gals0", "gals1";
2009 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2013 compatible = "mediatek,mt8195-smi-larb";
2015 mediatek,larb-id = <4>;
2019 clock-names = "apb", "smi";
2020 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2024 compatible = "mediatek,mt8195-iommu-vpp";
2032 clock-names = "bclk";
2033 #iommu-cells = <1>;
2034 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2037 wpesys: clock-controller@14e00000 {
2038 compatible = "mediatek,mt8195-wpesys";
2040 #clock-cells = <1>;
2043 wpesys_vpp0: clock-controller@14e02000 {
2044 compatible = "mediatek,mt8195-wpesys_vpp0";
2046 #clock-cells = <1>;
2049 wpesys_vpp1: clock-controller@14e03000 {
2050 compatible = "mediatek,mt8195-wpesys_vpp1";
2052 #clock-cells = <1>;
2056 compatible = "mediatek,mt8195-smi-larb";
2058 mediatek,larb-id = <7>;
2062 clock-names = "apb", "smi";
2063 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2067 compatible = "mediatek,mt8195-smi-larb";
2069 mediatek,larb-id = <8>;
2074 clock-names = "apb", "smi", "gals";
2075 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2079 compatible = "mediatek,mt8195-vppsys1", "syscon";
2081 #clock-cells = <1>;
2082 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2086 compatible = "mediatek,mt8195-vpp-mutex";
2089 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2091 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2095 compatible = "mediatek,mt8195-smi-larb";
2097 mediatek,larb-id = <5>;
2102 clock-names = "apb", "smi", "gals";
2103 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2107 compatible = "mediatek,mt8195-smi-larb";
2109 mediatek,larb-id = <6>;
2114 clock-names = "apb", "smi", "gals";
2115 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2118 imgsys: clock-controller@15000000 {
2119 compatible = "mediatek,mt8195-imgsys";
2121 #clock-cells = <1>;
2125 compatible = "mediatek,mt8195-smi-larb";
2127 mediatek,larb-id = <9>;
2132 clock-names = "apb", "smi", "gals";
2133 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2137 compatible = "mediatek,mt8195-smi-sub-common";
2142 clock-names = "apb", "smi", "gals0";
2144 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2148 compatible = "mediatek,mt8195-smi-sub-common";
2153 clock-names = "apb", "smi", "gals0";
2155 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2158 imgsys1_dip_top: clock-controller@15110000 {
2159 compatible = "mediatek,mt8195-imgsys1_dip_top";
2161 #clock-cells = <1>;
2165 compatible = "mediatek,mt8195-smi-larb";
2167 mediatek,larb-id = <10>;
2171 clock-names = "apb", "smi";
2172 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2175 imgsys1_dip_nr: clock-controller@15130000 {
2176 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2178 #clock-cells = <1>;
2181 imgsys1_wpe: clock-controller@15220000 {
2182 compatible = "mediatek,mt8195-imgsys1_wpe";
2184 #clock-cells = <1>;
2188 compatible = "mediatek,mt8195-smi-larb";
2190 mediatek,larb-id = <11>;
2194 clock-names = "apb", "smi";
2195 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2198 ipesys: clock-controller@15330000 {
2199 compatible = "mediatek,mt8195-ipesys";
2201 #clock-cells = <1>;
2205 compatible = "mediatek,mt8195-smi-larb";
2207 mediatek,larb-id = <12>;
2211 clock-names = "apb", "smi";
2212 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2215 camsys: clock-controller@16000000 {
2216 compatible = "mediatek,mt8195-camsys";
2218 #clock-cells = <1>;
2222 compatible = "mediatek,mt8195-smi-larb";
2224 mediatek,larb-id = <13>;
2229 clock-names = "apb", "smi", "gals";
2230 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2234 compatible = "mediatek,mt8195-smi-larb";
2236 mediatek,larb-id = <14>;
2240 clock-names = "apb", "smi";
2241 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2245 compatible = "mediatek,mt8195-smi-sub-common";
2250 clock-names = "apb", "smi", "gals0";
2252 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2256 compatible = "mediatek,mt8195-smi-sub-common";
2261 clock-names = "apb", "smi", "gals0";
2263 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2267 compatible = "mediatek,mt8195-smi-larb";
2269 mediatek,larb-id = <16>;
2273 clock-names = "apb", "smi";
2274 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2278 compatible = "mediatek,mt8195-smi-larb";
2280 mediatek,larb-id = <17>;
2284 clock-names = "apb", "smi";
2285 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2289 compatible = "mediatek,mt8195-smi-larb";
2291 mediatek,larb-id = <27>;
2295 clock-names = "apb", "smi";
2296 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2300 compatible = "mediatek,mt8195-smi-larb";
2302 mediatek,larb-id = <28>;
2306 clock-names = "apb", "smi";
2307 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2310 camsys_rawa: clock-controller@1604f000 {
2311 compatible = "mediatek,mt8195-camsys_rawa";
2313 #clock-cells = <1>;
2316 camsys_yuva: clock-controller@1606f000 {
2317 compatible = "mediatek,mt8195-camsys_yuva";
2319 #clock-cells = <1>;
2322 camsys_rawb: clock-controller@1608f000 {
2323 compatible = "mediatek,mt8195-camsys_rawb";
2325 #clock-cells = <1>;
2328 camsys_yuvb: clock-controller@160af000 {
2329 compatible = "mediatek,mt8195-camsys_yuvb";
2331 #clock-cells = <1>;
2334 camsys_mraw: clock-controller@16140000 {
2335 compatible = "mediatek,mt8195-camsys_mraw";
2337 #clock-cells = <1>;
2341 compatible = "mediatek,mt8195-smi-larb";
2343 mediatek,larb-id = <25>;
2348 clock-names = "apb", "smi", "gals";
2349 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2353 compatible = "mediatek,mt8195-smi-larb";
2355 mediatek,larb-id = <26>;
2359 clock-names = "apb", "smi";
2360 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2364 ccusys: clock-controller@17200000 {
2365 compatible = "mediatek,mt8195-ccusys";
2367 #clock-cells = <1>;
2371 compatible = "mediatek,mt8195-smi-larb";
2373 mediatek,larb-id = <18>;
2377 clock-names = "apb", "smi";
2378 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2381 video-codec@18000000 {
2382 compatible = "mediatek,mt8195-vcodec-dec";
2385 #address-cells = <2>;
2386 #size-cells = <2>;
2391 video-codec@2000 {
2392 compatible = "mediatek,mtk-vcodec-lat-soc";
2400 clock-names = "sel", "vdec", "lat", "top";
2401 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2402 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2403 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2406 video-codec@10000 {
2407 compatible = "mediatek,mtk-vcodec-lat";
2420 clock-names = "sel", "vdec", "lat", "top";
2421 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2422 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2423 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2426 video-codec@25000 {
2427 compatible = "mediatek,mtk-vcodec-core";
2444 clock-names = "sel", "vdec", "lat", "top";
2445 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2446 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2447 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2452 compatible = "mediatek,mt8195-smi-larb";
2454 mediatek,larb-id = <24>;
2458 clock-names = "apb", "smi";
2459 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2463 compatible = "mediatek,mt8195-smi-larb";
2465 mediatek,larb-id = <23>;
2469 clock-names = "apb", "smi";
2470 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2473 vdecsys_soc: clock-controller@1800f000 {
2474 compatible = "mediatek,mt8195-vdecsys_soc";
2476 #clock-cells = <1>;
2480 compatible = "mediatek,mt8195-smi-larb";
2482 mediatek,larb-id = <21>;
2486 clock-names = "apb", "smi";
2487 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2490 vdecsys: clock-controller@1802f000 {
2491 compatible = "mediatek,mt8195-vdecsys";
2493 #clock-cells = <1>;
2497 compatible = "mediatek,mt8195-smi-larb";
2499 mediatek,larb-id = <22>;
2503 clock-names = "apb", "smi";
2504 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2507 vdecsys_core1: clock-controller@1803f000 {
2508 compatible = "mediatek,mt8195-vdecsys_core1";
2510 #clock-cells = <1>;
2513 apusys_pll: clock-controller@190f3000 {
2514 compatible = "mediatek,mt8195-apusys_pll";
2516 #clock-cells = <1>;
2519 vencsys: clock-controller@1a000000 {
2520 compatible = "mediatek,mt8195-vencsys";
2522 #clock-cells = <1>;
2526 compatible = "mediatek,mt8195-smi-larb";
2528 mediatek,larb-id = <19>;
2532 clock-names = "apb", "smi";
2533 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2536 venc: video-codec@1a020000 {
2537 compatible = "mediatek,mt8195-vcodec-enc";
2551 clock-names = "venc_sel";
2552 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2553 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2554 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2555 #address-cells = <2>;
2556 #size-cells = <2>;
2559 jpgdec-master {
2560 compatible = "mediatek,mt8195-jpgdec";
2561 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2568 #address-cells = <2>;
2569 #size-cells = <2>;
2573 compatible = "mediatek,mt8195-jpgdec-hw";
2583 clock-names = "jpgdec";
2584 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2588 compatible = "mediatek,mt8195-jpgdec-hw";
2598 clock-names = "jpgdec";
2599 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2603 compatible = "mediatek,mt8195-jpgdec-hw";
2613 clock-names = "jpgdec";
2614 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2618 vencsys_core1: clock-controller@1b000000 {
2619 compatible = "mediatek,mt8195-vencsys_core1";
2621 #clock-cells = <1>;
2625 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2628 #clock-cells = <1>;
2629 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
2633 jpgenc-master {
2634 compatible = "mediatek,mt8195-jpgenc";
2635 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2640 #address-cells = <2>;
2641 #size-cells = <2>;
2645 compatible = "mediatek,mt8195-jpgenc-hw";
2653 clock-names = "jpgenc";
2654 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2658 compatible = "mediatek,mt8195-jpgenc-hw";
2666 clock-names = "jpgenc";
2667 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2672 compatible = "mediatek,mt8195-smi-larb";
2674 mediatek,larb-id = <20>;
2679 clock-names = "apb", "smi", "gals";
2680 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2684 compatible = "mediatek,mt8195-disp-ovl";
2687 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2690 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2694 compatible = "mediatek,mt8195-disp-rdma";
2697 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2700 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2704 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2707 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2709 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2713 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2716 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2718 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2722 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2725 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2727 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2731 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2734 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2736 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2740 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2743 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2745 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2749 compatible = "mediatek,mt8195-disp-dsc";
2752 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2754 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2758 compatible = "mediatek,mt8195-disp-merge";
2761 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2763 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2766 dp_intf0: dp-intf@1c015000 {
2767 compatible = "mediatek,mt8195-dp-intf";
2773 clock-names = "pixel", "engine", "pll";
2778 compatible = "mediatek,mt8195-disp-mutex";
2781 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2783 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
2784 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2788 compatible = "mediatek,mt8195-smi-larb";
2790 mediatek,larb-id = <0>;
2795 clock-names = "apb", "smi", "gals";
2796 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2800 compatible = "mediatek,mt8195-smi-larb";
2802 mediatek,larb-id = <1>;
2807 clock-names = "apb", "smi", "gals";
2808 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2812 compatible = "mediatek,mt8195-vdosys1", "syscon";
2815 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
2816 #clock-cells = <1>;
2817 #reset-cells = <1>;
2821 compatible = "mediatek,mt8195-smi-common-vdo";
2827 clock-names = "apb", "smi", "gals0", "gals1";
2828 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2833 compatible = "mediatek,mt8195-iommu-vdo";
2840 #iommu-cells = <1>;
2842 clock-names = "bclk";
2843 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2847 compatible = "mediatek,mt8195-disp-mutex";
2850 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2852 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
2853 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2857 compatible = "mediatek,mt8195-smi-larb";
2859 mediatek,larb-id = <2>;
2864 clock-names = "apb", "smi", "gals";
2865 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2869 compatible = "mediatek,mt8195-smi-larb";
2871 mediatek,larb-id = <3>;
2876 clock-names = "apb", "smi", "gals";
2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2880 vdo1_rdma0: dma-controller@1c104000 {
2881 compatible = "mediatek,mt8195-vdo1-rdma";
2885 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2887 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2888 #dma-cells = <1>;
2891 vdo1_rdma1: dma-controller@1c105000 {
2892 compatible = "mediatek,mt8195-vdo1-rdma";
2896 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2898 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2899 #dma-cells = <1>;
2902 vdo1_rdma2: dma-controller@1c106000 {
2903 compatible = "mediatek,mt8195-vdo1-rdma";
2907 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2909 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2910 #dma-cells = <1>;
2913 vdo1_rdma3: dma-controller@1c107000 {
2914 compatible = "mediatek,mt8195-vdo1-rdma";
2918 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2920 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2921 #dma-cells = <1>;
2924 vdo1_rdma4: dma-controller@1c108000 {
2925 compatible = "mediatek,mt8195-vdo1-rdma";
2929 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2931 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2932 #dma-cells = <1>;
2935 vdo1_rdma5: dma-controller@1c109000 {
2936 compatible = "mediatek,mt8195-vdo1-rdma";
2940 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2942 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2943 #dma-cells = <1>;
2946 vdo1_rdma6: dma-controller@1c10a000 {
2947 compatible = "mediatek,mt8195-vdo1-rdma";
2951 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2953 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2954 #dma-cells = <1>;
2957 vdo1_rdma7: dma-controller@1c10b000 {
2958 compatible = "mediatek,mt8195-vdo1-rdma";
2962 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2964 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2965 #dma-cells = <1>;
2968 merge1: vpp-merge@1c10c000 {
2969 compatible = "mediatek,mt8195-disp-merge";
2974 clock-names = "merge","merge_async";
2975 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2976 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2977 mediatek,merge-mute;
2981 merge2: vpp-merge@1c10d000 {
2982 compatible = "mediatek,mt8195-disp-merge";
2987 clock-names = "merge","merge_async";
2988 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2989 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2990 mediatek,merge-mute;
2994 merge3: vpp-merge@1c10e000 {
2995 compatible = "mediatek,mt8195-disp-merge";
3000 clock-names = "merge","merge_async";
3001 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3002 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3003 mediatek,merge-mute;
3007 merge4: vpp-merge@1c10f000 {
3008 compatible = "mediatek,mt8195-disp-merge";
3013 clock-names = "merge","merge_async";
3014 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3015 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3016 mediatek,merge-mute;
3020 merge5: vpp-merge@1c110000 {
3021 compatible = "mediatek,mt8195-disp-merge";
3026 clock-names = "merge","merge_async";
3027 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3028 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3029 mediatek,merge-fifo-en;
3033 dp_intf1: dp-intf@1c113000 {
3034 compatible = "mediatek,mt8195-dp-intf";
3037 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3041 clock-names = "pixel", "engine", "pll";
3045 ethdr0: hdr-engine@1c114000 {
3046 compatible = "mediatek,mt8195-disp-ethdr";
3054 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3056 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3076 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3080 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3089 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3093 edp_tx: edp-tx@1c500000 {
3094 compatible = "mediatek,mt8195-edp-tx";
3096 nvmem-cells = <&dp_calibration>;
3097 nvmem-cell-names = "dp_calibration_data";
3098 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3100 max-linkrate-mhz = <8100>;
3104 dp_tx: dp-tx@1c600000 {
3105 compatible = "mediatek,mt8195-dp-tx";
3107 nvmem-cells = <&dp_calibration>;
3108 nvmem-cell-names = "dp_calibration_data";
3109 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3111 max-linkrate-mhz = <8100>;
3116 thermal_zones: thermal-zones {
3117 cpu0-thermal {
3118 polling-delay = <1000>;
3119 polling-delay-passive = <250>;
3120 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3123 cpu0_alert: trip-alert {
3129 cpu0_crit: trip-crit {
3136 cooling-maps {
3139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3147 cpu1-thermal {
3148 polling-delay = <1000>;
3149 polling-delay-passive = <250>;
3150 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3153 cpu1_alert: trip-alert {
3159 cpu1_crit: trip-crit {
3166 cooling-maps {
3169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3177 cpu2-thermal {
3178 polling-delay = <1000>;
3179 polling-delay-passive = <250>;
3180 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3183 cpu2_alert: trip-alert {
3189 cpu2_crit: trip-crit {
3196 cooling-maps {
3199 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3207 cpu3-thermal {
3208 polling-delay = <1000>;
3209 polling-delay-passive = <250>;
3210 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3213 cpu3_alert: trip-alert {
3219 cpu3_crit: trip-crit {
3226 cooling-maps {
3229 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3237 cpu4-thermal {
3238 polling-delay = <1000>;
3239 polling-delay-passive = <250>;
3240 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3243 cpu4_alert: trip-alert {
3249 cpu4_crit: trip-crit {
3256 cooling-maps {
3259 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3267 cpu5-thermal {
3268 polling-delay = <1000>;
3269 polling-delay-passive = <250>;
3270 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3273 cpu5_alert: trip-alert {
3279 cpu5_crit: trip-crit {
3286 cooling-maps {
3289 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3297 cpu6-thermal {
3298 polling-delay = <1000>;
3299 polling-delay-passive = <250>;
3300 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3303 cpu6_alert: trip-alert {
3309 cpu6_crit: trip-crit {
3316 cooling-maps {
3319 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3327 cpu7-thermal {
3328 polling-delay = <1000>;
3329 polling-delay-passive = <250>;
3330 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3333 cpu7_alert: trip-alert {
3339 cpu7_crit: trip-crit {
3346 cooling-maps {
3349 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3357 vpu0-thermal {
3358 polling-delay = <1000>;
3359 polling-delay-passive = <250>;
3360 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3363 vpu0_alert: trip-alert {
3369 vpu0_crit: trip-crit {
3377 vpu1-thermal {
3378 polling-delay = <1000>;
3379 polling-delay-passive = <250>;
3380 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3383 vpu1_alert: trip-alert {
3389 vpu1_crit: trip-crit {
3397 gpu-thermal {
3398 polling-delay = <1000>;
3399 polling-delay-passive = <250>;
3400 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3403 gpu0_alert: trip-alert {
3409 gpu0_crit: trip-crit {
3417 gpu1-thermal {
3418 polling-delay = <1000>;
3419 polling-delay-passive = <250>;
3420 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3423 gpu1_alert: trip-alert {
3429 gpu1_crit: trip-crit {
3437 vdec-thermal {
3438 polling-delay = <1000>;
3439 polling-delay-passive = <250>;
3440 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3443 vdec_alert: trip-alert {
3449 vdec_crit: trip-crit {
3457 img-thermal {
3458 polling-delay = <1000>;
3459 polling-delay-passive = <250>;
3460 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3463 img_alert: trip-alert {
3469 img_crit: trip-crit {
3477 infra-thermal {
3478 polling-delay = <1000>;
3479 polling-delay-passive = <250>;
3480 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3483 infra_alert: trip-alert {
3489 infra_crit: trip-crit {
3497 cam0-thermal {
3498 polling-delay = <1000>;
3499 polling-delay-passive = <250>;
3500 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3503 cam0_alert: trip-alert {
3509 cam0_crit: trip-crit {
3517 cam1-thermal {
3518 polling-delay = <1000>;
3519 polling-delay-passive = <250>;
3520 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3523 cam1_alert: trip-alert {
3529 cam1_crit: trip-crit {