Lines Matching +full:1 +full:b040000
50 #address-cells = <1>;
134 performance-domains = <&performance 1>;
153 performance-domains = <&performance 1>;
172 performance-domains = <&performance 1>;
191 performance-domains = <&performance 1>;
335 clock-mult = <1>;
356 #performance-domain-cells = <1>;
465 #redistributor-regions = <1>;
477 ppi_cluster1: interrupt-partition-1 {
486 #clock-cells = <1>;
492 #clock-cells = <1>;
493 #reset-cells = <1>;
499 #clock-cells = <1>;
530 #address-cells = <1>;
532 #power-domain-cells = <1>;
537 #address-cells = <1>;
539 #power-domain-cells = <1>;
547 #address-cells = <1>;
549 #power-domain-cells = <1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
616 #address-cells = <1>;
618 #power-domain-cells = <1>;
645 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
649 #address-cells = <1>;
651 #power-domain-cells = <1>;
659 "vppsys1-1";
670 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
707 "vdosys1-1", "vdosys1-2";
709 #address-cells = <1>;
711 #power-domain-cells = <1>;
737 clock-names = "img-0", "img-1";
739 #address-cells = <1>;
741 #power-domain-cells = <1>;
753 clock-names = "ipe", "ipe-0", "ipe-1";
766 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
769 #address-cells = <1>;
771 #power-domain-cells = <1>;
833 #address-cells = <1>;
836 #power-domain-cells = <1>;
857 #reset-cells = <1>;
863 #clock-cells = <1>;
909 #iommu-cells = <1>;
941 #clock-cells = <1>;
1096 #io-channel-cells = <1>;
1103 #clock-cells = <1>;
1109 #address-cells = <1>;
1127 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128 #thermal-sensor-cells = <1>;
1157 #address-cells = <1>;
1171 #address-cells = <1>;
1185 #address-cells = <1>;
1199 #address-cells = <1>;
1213 #address-cells = <1>;
1281 #address-cells = <1>;
1413 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1414 #thermal-sensor-cells = <1>;
1526 #interrupt-cells = <1>;
1528 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1529 <0 0 0 2 &pcie_intc0 1>,
1537 #interrupt-cells = <1>;
1578 #interrupt-cells = <1>;
1580 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1581 <0 0 0 2 &pcie_intc1 1>,
1589 #interrupt-cells = <1>;
1602 #address-cells = <1>;
1610 #address-cells = <1>;
1611 #size-cells = <1>;
1612 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1624 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1636 u2_intr_p0: usb2-intr-p0@188,1 {
1644 u2_intr_p2: usb2-intr-p2@189,1 {
1652 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1660 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1668 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1680 dp_calibration: dp-data@1ac {
1683 lvts_efuse_data1: lvts1-calib@1bc {
1686 lvts_efuse_data2: lvts2-calib@1d0 {
1693 #address-cells = <1>;
1694 #size-cells = <1>;
1702 #phy-cells = <1>;
1708 #address-cells = <1>;
1709 #size-cells = <1>;
1717 #phy-cells = <1>;
1727 clock-div = <1>;
1731 #address-cells = <1>;
1742 clock-div = <1>;
1746 #address-cells = <1>;
1757 clock-div = <1>;
1761 #address-cells = <1>;
1769 #clock-cells = <1>;
1778 clock-div = <1>;
1782 #address-cells = <1>;
1793 clock-div = <1>;
1797 #address-cells = <1>;
1808 clock-div = <1>;
1812 #address-cells = <1>;
1823 clock-div = <1>;
1827 #address-cells = <1>;
1838 clock-div = <1>;
1842 #address-cells = <1>;
1850 #clock-cells = <1>;
1855 #address-cells = <1>;
1856 #size-cells = <1>;
1866 #phy-cells = <1>;
1878 #phy-cells = <1>;
1884 #address-cells = <1>;
1885 #size-cells = <1>;
1894 #phy-cells = <1>;
1906 #phy-cells = <1>;
1959 #clock-cells = <1>;
1965 #clock-cells = <1>;
2032 #iommu-cells = <1>;
2039 #clock-cells = <1>;
2045 #clock-cells = <1>;
2051 #clock-cells = <1>;
2080 #clock-cells = <1>;
2120 #clock-cells = <1>;
2160 #clock-cells = <1>;
2177 #clock-cells = <1>;
2183 #clock-cells = <1>;
2200 #clock-cells = <1>;
2217 #clock-cells = <1>;
2312 #clock-cells = <1>;
2318 #clock-cells = <1>;
2324 #clock-cells = <1>;
2330 #clock-cells = <1>;
2336 #clock-cells = <1>;
2366 #clock-cells = <1>;
2475 #clock-cells = <1>;
2492 #clock-cells = <1>;
2509 #clock-cells = <1>;
2515 #clock-cells = <1>;
2518 vencsys: clock-controller@1a000000 {
2521 #clock-cells = <1>;
2524 larb19: larb@1a010000 {
2535 venc: video-codec@1a020000 {
2571 jpgdec@1a040000 {
2586 jpgdec@1a050000 {
2601 jpgdec@1b040000 {
2617 vencsys_core1: clock-controller@1b000000 {
2620 #clock-cells = <1>;
2623 vdosys0: syscon@1c01a000 {
2627 #clock-cells = <1>;
2643 jpgenc@1a030000 {
2656 jpgenc@1b030000 {
2670 larb20: larb@1b010000 {
2682 ovl0: ovl@1c000000 {
2692 rdma0: rdma@1c002000 {
2702 color0: color@1c003000 {
2711 ccorr0: ccorr@1c004000 {
2720 aal0: aal@1c005000 {
2729 gamma0: gamma@1c006000 {
2738 dither0: dither@1c007000 {
2747 dsc0: dsc@1c009000 {
2756 merge0: merge@1c014000 {
2765 dp_intf0: dp-intf@1c015000 {
2776 mutex: mutex@1c016000 {
2786 larb0: larb@1c018000 {
2798 larb1: larb@1c019000 {
2801 mediatek,larb-id = <1>;
2810 vdosys1: syscon@1c100000 {
2813 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
2815 #clock-cells = <1>;
2816 #reset-cells = <1>;
2819 smi_common_vdo: smi@1c01b000 {
2831 iommu_vdo: iommu@1c01f000 {
2839 #iommu-cells = <1>;
2845 mutex1: mutex@1c101000 {
2855 larb2: larb@1c102000 {
2867 larb3: larb@1c103000 {
2879 vdo1_rdma0: dma-controller@1c104000 {
2887 #dma-cells = <1>;
2890 vdo1_rdma1: dma-controller@1c105000 {
2898 #dma-cells = <1>;
2901 vdo1_rdma2: dma-controller@1c106000 {
2909 #dma-cells = <1>;
2912 vdo1_rdma3: dma-controller@1c107000 {
2920 #dma-cells = <1>;
2923 vdo1_rdma4: dma-controller@1c108000 {
2931 #dma-cells = <1>;
2934 vdo1_rdma5: dma-controller@1c109000 {
2942 #dma-cells = <1>;
2945 vdo1_rdma6: dma-controller@1c10a000 {
2953 #dma-cells = <1>;
2956 vdo1_rdma7: dma-controller@1c10b000 {
2964 #dma-cells = <1>;
2967 merge1: vpp-merge@1c10c000 {
2980 merge2: vpp-merge@1c10d000 {
2993 merge3: vpp-merge@1c10e000 {
3006 merge4: vpp-merge@1c10f000 {
3019 merge5: vpp-merge@1c110000 {
3032 dp_intf1: dp-intf@1c113000 {
3044 ethdr0: hdr-engine@1c114000 {
3092 edp_tx: edp-tx@1c500000 {
3103 dp_tx: dp-tx@1c600000 {