Lines Matching +full:0 +full:x1100a000
293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
517 arm,psci-suspend-param = <0x00010001>;
523 CLUSTER_SLEEP0: cluster-sleep-0 {
526 arm,psci-suspend-param = <0x01010001>;
534 arm,psci-suspend-param = <0x01010001>;
560 gpu_opp_table: opp-table-0 {
664 #clock-cells = <0>;
673 #clock-cells = <0>;
681 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
682 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
683 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
684 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
696 reg = <0 0x08000000 0 0x0010>;
707 reg = <0 0x0c000000 0 0x40000>, /* GICD */
708 <0 0x0c100000 0 0x200000>, /* GICR */
709 <0 0x0c400000 0 0x2000>, /* GICC */
710 <0 0x0c410000 0 0x1000>, /* GICH */
711 <0 0x0c420000 0 0x2000>; /* GICV */
713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
715 ppi_cluster0: interrupt-partition-0 {
726 reg = <0 0x0c530000 0 0x1000>;
736 reg = <0 0x0c530a80 0 0x50>;
741 reg = <0x0 0xd410000 0x0 0x1000>;
749 reg = <0x0 0xd510000 0x0 0x1000>;
757 reg = <0x0 0xd610000 0x0 0x1000>;
765 reg = <0x0 0xd710000 0x0 0x1000>;
773 reg = <0x0 0xd810000 0x0 0x1000>;
781 reg = <0x0 0xd910000 0x0 0x1000>;
789 reg = <0x0 0xda10000 0x0 0x1000>;
797 reg = <0x0 0xdb10000 0x0 0x1000>;
805 reg = <0 0x10000000 0 0x1000>;
811 reg = <0 0x10001000 0 0x1000>;
818 reg = <0 0x10003000 0 0x1000>;
824 reg = <0 0x10005000 0 0x1000>,
825 <0 0x11f20000 0 0x1000>,
826 <0 0x11e80000 0 0x1000>,
827 <0 0x11e70000 0 0x1000>,
828 <0 0x11e90000 0 0x1000>,
829 <0 0x11d30000 0 0x1000>,
830 <0 0x11d20000 0 0x1000>,
831 <0 0x11c50000 0 0x1000>,
832 <0 0x11f30000 0 0x1000>,
833 <0 0x1000b000 0 0x1000>;
840 gpio-ranges = <&pio 0 0 192>;
848 reg = <0 0x10006000 0 0x1000>;
854 #size-cells = <0>;
864 #power-domain-cells = <0>;
870 #power-domain-cells = <0>;
878 #size-cells = <0>;
884 #size-cells = <0>;
889 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
900 #power-domain-cells = <0>;
918 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
924 #size-cells = <0>;
937 clock-names = "cam", "cam-0", "cam-1",
942 #power-domain-cells = <0>;
950 clock-names = "isp", "isp-0", "isp-1";
953 #power-domain-cells = <0>;
959 #power-domain-cells = <0>;
965 #power-domain-cells = <0>;
978 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
983 #size-cells = <0>;
991 #power-domain-cells = <0>;
999 #power-domain-cells = <0>;
1008 reg = <0 0x10007000 0 0x100>;
1014 reg = <0 0x1000c000 0 0x1000>;
1020 reg = <0 0x1000d000 0 0x1000>;
1031 reg = <0 0x10010000 0 0x1000>;
1040 reg = <0 0x10500000 0 0x80000>,
1041 <0 0x105c0000 0 0x19080>;
1053 reg = <0 0x10017000 0 0x1000>;
1060 reg = <0 0x10205000 0 0x1000>;
1069 reg = <0 0x10238000 0 0x4000>;
1079 reg = <0 0x11001000 0 0x1000>;
1089 reg = <0 0x11002000 0 0x1000>;
1099 reg = <0 0x11003000 0 0x1000>;
1109 reg = <0 0x11004000 0 0x1000>;
1118 reg = <0 0x11005000 0 0x1000>,
1119 <0 0x11000600 0 0x80>;
1126 #size-cells = <0>;
1132 reg = <0 0x11007000 0 0x1000>,
1133 <0 0x11000080 0 0x80>;
1140 #size-cells = <0>;
1146 reg = <0 0x11008000 0 0x1000>,
1147 <0 0x11000100 0 0x80>;
1155 #size-cells = <0>;
1161 reg = <0 0x11009000 0 0x1000>,
1162 <0 0x11000280 0 0x80>;
1170 #size-cells = <0>;
1177 #size-cells = <0>;
1178 reg = <0 0x1100a000 0 0x1000>;
1189 reg = <0 0x1100b000 0 0x1000>;
1202 reg = <0 0x1100b000 0 0x1000>;
1207 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
1216 reg = <0 0x1100e000 0 0x1000>;
1227 reg = <0 0x11006000 0 0x1000>;
1241 reg = <0 0x1100f000 0 0x1000>,
1242 <0 0x11000400 0 0x80>;
1249 #size-cells = <0>;
1256 #size-cells = <0>;
1257 reg = <0 0x11010000 0 0x1000>;
1268 reg = <0 0x11011000 0 0x1000>,
1269 <0 0x11000480 0 0x80>;
1276 #size-cells = <0>;
1283 #size-cells = <0>;
1284 reg = <0 0x11012000 0 0x1000>;
1296 #size-cells = <0>;
1297 reg = <0 0x11013000 0 0x1000>;
1308 reg = <0 0x11014000 0 0x1000>,
1309 <0 0x11000180 0 0x80>;
1317 #size-cells = <0>;
1323 reg = <0 0x11015000 0 0x1000>,
1324 <0 0x11000300 0 0x80>;
1332 #size-cells = <0>;
1338 reg = <0 0x11016000 0 0x1000>,
1339 <0 0x11000500 0 0x80>;
1347 #size-cells = <0>;
1353 reg = <0 0x11017000 0 0x1000>,
1354 <0 0x11000580 0 0x80>;
1362 #size-cells = <0>;
1369 #size-cells = <0>;
1370 reg = <0 0x11018000 0 0x1000>;
1382 #size-cells = <0>;
1383 reg = <0 0x11019000 0 0x1000>;
1394 reg = <0 0x1101a000 0 0x1000>,
1395 <0 0x11000680 0 0x80>;
1402 #size-cells = <0>;
1408 reg = <0 0x1101b000 0 0x1000>,
1409 <0 0x11000700 0 0x80>;
1416 #size-cells = <0>;
1422 reg = <0 0x11201000 0 0x2e00>,
1423 <0 0x11203e00 0 0x0100>;
1431 mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1440 reg = <0 0x11200000 0 0x1000>;
1452 reg = <0 0x11220000 0 0x1000>;
1550 reg = <0 0x11230000 0 0x1000>,
1551 <0 0x11f50000 0 0x1000>;
1562 reg = <0 0x11240000 0 0x1000>,
1563 <0 0x11e10000 0 0x1000>;
1574 reg = <0 0x11e50000 0 0x1000>;
1576 #clock-cells = <0>;
1577 #phy-cells = <0>;
1586 reg = <0 0x11f10000 0 0x1000>;
1590 reg = <0x180 0xc>;
1594 reg = <0x190 0xc>;
1598 reg = <0x580 0x64>;
1607 ranges = <0 0 0x11f40000 0x1000>;
1610 u2port0: usb-phy@0 {
1611 reg = <0x0 0x700>;
1620 reg = <0x0700 0x900>;
1630 reg = <0 0x13000000 0 0x1000>;
1637 reg = <0 0x13040000 0 0x4000>;
1657 reg = <0 0x14000000 0 0x1000>;
1660 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1662 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1667 reg = <0 0x14001000 0 0x1000>;
1668 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1675 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
1676 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
1682 reg = <0 0x14003000 0 0x1000>;
1683 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1691 reg = <0 0x14004000 0 0x1000>;
1692 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1700 reg = <0 0x14005000 0 0x1000>;
1701 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1712 reg = <0 0x14006000 0 0x1000>;
1713 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1723 reg = <0 0x14008000 0 0x1000>;
1728 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1733 reg = <0 0x14009000 0 0x1000>;
1738 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1743 reg = <0 0x1400a000 0 0x1000>;
1748 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1753 reg = <0 0x1400b000 0 0x1000>;
1759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1764 reg = <0 0x1400c000 0 0x1000>;
1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1776 reg = <0 0x1400e000 0 0x1000>;
1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1785 reg = <0 0x1400f000 0 0x1000>;
1789 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1794 reg = <0 0x14010000 0 0x1000>;
1798 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1803 reg = <0 0x14011000 0 0x1000>;
1807 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1812 reg = <0 0x14012000 0 0x1000>;
1816 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1821 reg = <0 0x14014000 0 0x1000>;
1836 reg = <0 0x14016000 0 0x1000>;
1841 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1846 reg = <0 0x14017000 0 0x1000>;
1856 reg = <0 0x14019000 0 0x1000>;
1867 reg = <0 0x1401c000 0 0x1000>;
1868 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
1876 reg = <0 0x15020000 0 0x1000>;
1882 reg = <0 0x15021000 0 0x1000>;
1892 reg = <0 0x1502f000 0 0x1000>;
1902 reg = <0 0x16000000 0 0x1000>;
1908 reg = <0 0x16010000 0 0x1000>;
1917 reg = <0 0x17000000 0 0x1000>;
1923 reg = <0 0x17010000 0 0x1000>;
1933 reg = <0 0x17030000 0 0x1000>;
1944 reg = <0 0x19000000 0 0x1000>;
1950 reg = <0 0x19010000 0 0x1000>;
1956 reg = <0 0x19180000 0 0x1000>;
1962 reg = <0 0x19280000 0 0x1000>;
1968 reg = <0 0x1a000000 0 0x1000>;
1974 reg = <0 0x1a001000 0 0x1000>;
1984 reg = <0 0x1a002000 0 0x1000>;
1997 thermal-sensors = <&thermal 0>;
2060 polling-delay-passive = <0>;
2061 polling-delay = <0>;
2069 polling-delay-passive = <0>;
2070 polling-delay = <0>;
2078 polling-delay-passive = <0>;
2079 polling-delay = <0>;
2087 polling-delay-passive = <0>;
2088 polling-delay = <0>;
2096 polling-delay-passive = <0>;
2097 polling-delay = <0>;
2105 polling-delay-passive = <0>;
2106 polling-delay = <0>;