Lines Matching +full:0 +full:x00030000
20 * the synchronous boot mode is selected. When ASDO is "0" (i.e
24 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
25 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
26 * decoded at 0xf0000000.
35 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
36 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
37 #define EP93XX_CS1_PHYS_BASE 0x10000000
38 #define EP93XX_CS2_PHYS_BASE 0x20000000
39 #define EP93XX_CS3_PHYS_BASE 0x30000000
40 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
41 #define EP93XX_CS6_PHYS_BASE 0x60000000
42 #define EP93XX_CS7_PHYS_BASE 0x70000000
43 #define EP93XX_SDCE0_PHYS_BASE 0xc0000000
44 #define EP93XX_SDCE1_PHYS_BASE 0xd0000000
45 #define EP93XX_SDCE2_PHYS_BASE 0xe0000000
46 #define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
47 #define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
50 #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
52 #define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
53 #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
55 #define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
56 #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
58 #define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
59 #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
61 #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
63 #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
65 #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
67 #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
69 #define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
70 #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
72 #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
74 #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
77 #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
79 #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
80 #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
82 #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
84 #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
85 #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
87 #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
88 #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
90 #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
92 #define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
93 #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
95 #define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
96 #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
97 #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
99 #define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
100 #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
102 #define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
103 #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
105 #define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
106 #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
109 #define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
111 #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
112 #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
128 #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
129 #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
130 #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
132 #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
135 #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
165 #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
166 #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
171 #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
176 #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
180 #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
184 #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
185 #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
186 #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
195 #define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
196 #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
204 ep93xx_devcfg_set_clear(bits, 0x00); in ep93xx_devcfg_set_bits()
209 ep93xx_devcfg_set_clear(0x00, bits); in ep93xx_devcfg_clear_bits()