Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
360 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
515 gcc: clock-controller@900000 { label
516 compatible = "qcom,gcc-ipq8064", "syscon";
573 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
583 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
598 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
620 clocks = <&gcc USB30_0_MASTER_CLK>;
625 resets = <&gcc USB30_0_MASTER_RESET>;
644 clocks = <&gcc USB30_0_UTMI_CLK>;
654 clocks = <&gcc USB30_0_MASTER_CLK>;
666 clocks = <&gcc USB30_1_MASTER_CLK>;
671 resets = <&gcc USB30_1_MASTER_RESET>;
690 clocks = <&gcc USB30_1_UTMI_CLK>;
700 clocks = <&gcc USB30_1_MASTER_CLK>;
711 clocks = <&gcc SDC3_H_CLK>;
721 clocks = <&gcc SDC1_H_CLK>;
739 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
758 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
775 clocks = <&gcc GSBI1_H_CLK>;
790 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
800 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
813 clocks = <&gcc GSBI2_H_CLK>;
827 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
837 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
850 clocks = <&gcc GSBI4_H_CLK>;
864 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
874 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
887 clocks = <&gcc GSBI6_H_CLK>;
902 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
916 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
931 clocks = <&gcc GSBI7_H_CLK>;
943 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
953 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
969 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
972 resets = <&gcc ADM0_RESET>,
973 <&gcc ADM0_PBUS_RESET>,
974 <&gcc ADM0_C0_RESET>,
975 <&gcc ADM0_C1_RESET>,
976 <&gcc ADM0_C2_RESET>;
987 clocks = <&gcc GSBI5_H_CLK>;
1002 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1012 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1025 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1042 clocks = <&gcc PRNG_CLK>;
1053 clocks = <&gcc EBI2_CLK>,
1054 <&gcc EBI2_AON_CLK>;
1072 clocks = <&gcc SATA_PHY_CFG_CLK>;
1105 clocks = <&gcc PCIE_A_CLK>,
1106 <&gcc PCIE_H_CLK>,
1107 <&gcc PCIE_PHY_CLK>,
1108 <&gcc PCIE_AUX_CLK>,
1109 <&gcc PCIE_ALT_REF_CLK>;
1112 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1115 resets = <&gcc PCIE_ACLK_RESET>,
1116 <&gcc PCIE_HCLK_RESET>,
1117 <&gcc PCIE_POR_RESET>,
1118 <&gcc PCIE_PCI_RESET>,
1119 <&gcc PCIE_PHY_RESET>,
1120 <&gcc PCIE_EXT_RESET>;
1156 clocks = <&gcc PCIE_1_A_CLK>,
1157 <&gcc PCIE_1_H_CLK>,
1158 <&gcc PCIE_1_PHY_CLK>,
1159 <&gcc PCIE_1_AUX_CLK>,
1160 <&gcc PCIE_1_ALT_REF_CLK>;
1163 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1166 resets = <&gcc PCIE_1_ACLK_RESET>,
1167 <&gcc PCIE_1_HCLK_RESET>,
1168 <&gcc PCIE_1_POR_RESET>,
1169 <&gcc PCIE_1_PCI_RESET>,
1170 <&gcc PCIE_1_PHY_RESET>,
1171 <&gcc PCIE_1_EXT_RESET>;
1207 clocks = <&gcc PCIE_2_A_CLK>,
1208 <&gcc PCIE_2_H_CLK>,
1209 <&gcc PCIE_2_PHY_CLK>,
1210 <&gcc PCIE_2_AUX_CLK>,
1211 <&gcc PCIE_2_ALT_REF_CLK>;
1214 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1217 resets = <&gcc PCIE_2_ACLK_RESET>,
1218 <&gcc PCIE_2_HCLK_RESET>,
1219 <&gcc PCIE_2_POR_RESET>,
1220 <&gcc PCIE_2_PCI_RESET>,
1221 <&gcc PCIE_2_PHY_RESET>,
1222 <&gcc PCIE_2_EXT_RESET>;
1265 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1266 <&gcc SATA_H_CLK>,
1267 <&gcc SATA_A_CLK>,
1268 <&gcc SATA_RXOOB_CLK>,
1269 <&gcc SATA_PMALIVE_CLK>;
1273 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1295 clocks = <&gcc GMAC_CORE1_CLK>;
1298 resets = <&gcc GMAC_CORE1_RESET>,
1299 <&gcc GMAC_AHB_RESET>;
1319 clocks = <&gcc GMAC_CORE2_CLK>;
1322 resets = <&gcc GMAC_CORE2_RESET>,
1323 <&gcc GMAC_AHB_RESET>;
1343 clocks = <&gcc GMAC_CORE3_CLK>;
1346 resets = <&gcc GMAC_CORE3_RESET>,
1347 <&gcc GMAC_AHB_RESET>;
1367 clocks = <&gcc GMAC_CORE4_CLK>;
1370 resets = <&gcc GMAC_CORE4_RESET>,
1371 <&gcc GMAC_AHB_RESET>;