Lines Matching refs:gcc

8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
187 gcc: clock-controller@1800000 { label
188 compatible = "qcom,gcc-ipq4019";
200 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
234 <&gcc GCC_SDCC1_APPS_CLK>,
246 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
257 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
258 <&gcc GCC_BLSP1_AHB_CLK>;
271 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
272 <&gcc GCC_BLSP1_AHB_CLK>;
285 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
286 <&gcc GCC_BLSP1_AHB_CLK>;
299 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
300 <&gcc GCC_BLSP1_AHB_CLK>;
313 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
324 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
325 <&gcc GCC_CRYPTO_AXI_CLK>,
326 <&gcc GCC_CRYPTO_CLK>;
388 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
389 <&gcc GCC_BLSP1_AHB_CLK>;
400 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
401 <&gcc GCC_BLSP1_AHB_CLK>;
445 clocks = <&gcc GCC_PCIE_AHB_CLK>,
446 <&gcc GCC_PCIE_AXI_M_CLK>,
447 <&gcc GCC_PCIE_AXI_S_CLK>;
452 resets = <&gcc PCIE_AXI_M_ARES>,
453 <&gcc PCIE_AXI_S_ARES>,
454 <&gcc PCIE_PIPE_ARES>,
455 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
456 <&gcc PCIE_AXI_S_XPU_ARES>,
457 <&gcc PCIE_PARF_XPU_ARES>,
458 <&gcc PCIE_PHY_ARES>,
459 <&gcc PCIE_AXI_M_STICKY_ARES>,
460 <&gcc PCIE_PIPE_STICKY_ARES>,
461 <&gcc PCIE_PWR_ARES>,
462 <&gcc PCIE_AHB_ARES>,
463 <&gcc PCIE_PHY_AHB_ARES>;
484 clocks = <&gcc GCC_QPIC_CLK>;
496 clocks = <&gcc GCC_QPIC_CLK>,
497 <&gcc GCC_QPIC_AHB_CLK>;
518 resets = <&gcc WIFI0_CPU_INIT_RESET>,
519 <&gcc WIFI0_RADIO_SRIF_RESET>,
520 <&gcc WIFI0_RADIO_WARM_RESET>,
521 <&gcc WIFI0_RADIO_COLD_RESET>,
522 <&gcc WIFI0_CORE_WARM_RESET>,
523 <&gcc WIFI0_CORE_COLD_RESET>;
527 clocks = <&gcc GCC_WCSS2G_CLK>,
528 <&gcc GCC_WCSS2G_REF_CLK>,
529 <&gcc GCC_WCSS2G_RTC_CLK>;
560 resets = <&gcc WIFI1_CPU_INIT_RESET>,
561 <&gcc WIFI1_RADIO_SRIF_RESET>,
562 <&gcc WIFI1_RADIO_WARM_RESET>,
563 <&gcc WIFI1_RADIO_COLD_RESET>,
564 <&gcc WIFI1_CORE_WARM_RESET>,
565 <&gcc WIFI1_CORE_COLD_RESET>;
569 clocks = <&gcc GCC_WCSS5G_CLK>,
570 <&gcc GCC_WCSS5G_REF_CLK>,
571 <&gcc GCC_WCSS5G_RTC_CLK>;
632 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
642 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
652 clocks = <&gcc GCC_USB3_MASTER_CLK>,
653 <&gcc GCC_USB3_SLEEP_CLK>,
654 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
674 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
684 clocks = <&gcc GCC_USB2_MASTER_CLK>,
685 <&gcc GCC_USB2_SLEEP_CLK>,
686 <&gcc GCC_USB2_MOCK_UTMI_CLK>;