Lines Matching +full:bootloader +full:- +full:config
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
150 The ARM series is a line of low-power-consumption RISC chip designs
152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
153 manufactured, but legacy ARM-based PC hardware remains popular in
157 config ARM_HAS_GROUP_RELOCS
164 supported in LLD until version 14. The combined range is -/+ 256 MiB,
168 config ARM_DMA_USE_IOMMU
174 config ARM_DMA_IOMMU_ALIGNMENT
193 config SYS_SUPPORTS_APM_EMULATION
196 config HAVE_TCM
200 config HAVE_PROC_CPU
203 config NO_IOPORT_MAP
206 config SBUS
209 config STACKTRACE_SUPPORT
213 config LOCKDEP_SUPPORT
217 config ARCH_HAS_ILOG2_U32
220 config ARCH_HAS_ILOG2_U64
223 config ARCH_HAS_BANDGAP
226 config FIX_EARLYCON_MEM
229 config GENERIC_HWEIGHT
233 config GENERIC_CALIBRATE_DELAY
237 config ARCH_MAY_HAVE_PC_FDC
240 config ARCH_SUPPORTS_UPROBES
243 config GENERIC_ISA_DMA
246 config FIQ
249 config ARCH_MTD_XIP
252 config ARM_PATCH_PHYS_VIRT
257 Patch phys-to-virt and virt-to-phys translation functions at
261 This can only be used with non-XIP MMU kernels where the base
268 config NEED_MACH_IO_H
275 config NEED_MACH_MEMORY_H
282 config PHYS_OFFSET
295 config GENERIC_BUG
299 config PGTABLE_LEVELS
306 config MMU
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
313 config ARM_SINGLE_ARMV7M
319 config ARCH_MMAP_RND_BITS_MIN
322 config ARCH_MMAP_RND_BITS_MAX
327 config ARCH_MULTIPLATFORM
347 config ARCH_MULTI_V4
350 # https://github.com/llvm/llvm-project/issues/50764
355 config ARCH_MULTI_V4T
358 # https://github.com/llvm/llvm-project/issues/50764
365 config ARCH_MULTI_V5
373 config ARCH_MULTI_V4_V5
376 config ARCH_MULTI_V6
381 config ARCH_MULTI_V7
382 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
388 config ARCH_MULTI_V6_V7
392 config ARCH_MULTI_CPU_AUTO
398 config ARCH_VIRT
409 config ARCH_AIROHA
421 # This is sorted alphabetically by mach-* pathname. However, plat-*
423 # plat- suffix) or along side the corresponding mach-* source.
425 source "arch/arm/mach-actions/Kconfig"
427 source "arch/arm/mach-alpine/Kconfig"
429 source "arch/arm/mach-artpec/Kconfig"
431 source "arch/arm/mach-asm9260/Kconfig"
433 source "arch/arm/mach-aspeed/Kconfig"
435 source "arch/arm/mach-at91/Kconfig"
437 source "arch/arm/mach-axxia/Kconfig"
439 source "arch/arm/mach-bcm/Kconfig"
441 source "arch/arm/mach-berlin/Kconfig"
443 source "arch/arm/mach-clps711x/Kconfig"
445 source "arch/arm/mach-davinci/Kconfig"
447 source "arch/arm/mach-digicolor/Kconfig"
449 source "arch/arm/mach-dove/Kconfig"
451 source "arch/arm/mach-ep93xx/Kconfig"
453 source "arch/arm/mach-exynos/Kconfig"
455 source "arch/arm/mach-footbridge/Kconfig"
457 source "arch/arm/mach-gemini/Kconfig"
459 source "arch/arm/mach-highbank/Kconfig"
461 source "arch/arm/mach-hisi/Kconfig"
463 source "arch/arm/mach-hpe/Kconfig"
465 source "arch/arm/mach-imx/Kconfig"
467 source "arch/arm/mach-ixp4xx/Kconfig"
469 source "arch/arm/mach-keystone/Kconfig"
471 source "arch/arm/mach-lpc32xx/Kconfig"
473 source "arch/arm/mach-mediatek/Kconfig"
475 source "arch/arm/mach-meson/Kconfig"
477 source "arch/arm/mach-milbeaut/Kconfig"
479 source "arch/arm/mach-mmp/Kconfig"
481 source "arch/arm/mach-moxart/Kconfig"
483 source "arch/arm/mach-mstar/Kconfig"
485 source "arch/arm/mach-mv78xx0/Kconfig"
487 source "arch/arm/mach-mvebu/Kconfig"
489 source "arch/arm/mach-mxs/Kconfig"
491 source "arch/arm/mach-nomadik/Kconfig"
493 source "arch/arm/mach-npcm/Kconfig"
495 source "arch/arm/mach-nspire/Kconfig"
497 source "arch/arm/mach-omap1/Kconfig"
499 source "arch/arm/mach-omap2/Kconfig"
501 source "arch/arm/mach-orion5x/Kconfig"
503 source "arch/arm/mach-pxa/Kconfig"
505 source "arch/arm/mach-qcom/Kconfig"
507 source "arch/arm/mach-rda/Kconfig"
509 source "arch/arm/mach-realtek/Kconfig"
511 source "arch/arm/mach-rpc/Kconfig"
513 source "arch/arm/mach-rockchip/Kconfig"
515 source "arch/arm/mach-s3c/Kconfig"
517 source "arch/arm/mach-s5pv210/Kconfig"
519 source "arch/arm/mach-sa1100/Kconfig"
521 source "arch/arm/mach-shmobile/Kconfig"
523 source "arch/arm/mach-socfpga/Kconfig"
525 source "arch/arm/mach-spear/Kconfig"
527 source "arch/arm/mach-sti/Kconfig"
529 source "arch/arm/mach-stm32/Kconfig"
531 source "arch/arm/mach-sunplus/Kconfig"
533 source "arch/arm/mach-sunxi/Kconfig"
535 source "arch/arm/mach-tegra/Kconfig"
537 source "arch/arm/mach-uniphier/Kconfig"
539 source "arch/arm/mach-ux500/Kconfig"
541 source "arch/arm/mach-versatile/Kconfig"
543 source "arch/arm/mach-vt8500/Kconfig"
545 source "arch/arm/mach-zynq/Kconfig"
547 # ARMv7-M architecture
548 config ARCH_LPC18XX
556 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
559 config ARCH_MPS2
565 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
566 with a range of available cores like Cortex-M3/M4/M7.
572 config ARCH_ACORN
575 config PLAT_ORION
581 config PLAT_ORION_LEGACY
585 config PLAT_VERSATILE
590 config IWMMXT
599 source "arch/arm/Kconfig-nommu"
602 config PJ4B_ERRATA_4742
616 config ARM_ERRATA_326103
617 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
620 Executing a SWP instruction to read-only memory does not set bit 11
625 config ARM_ERRATA_411920
634 config ARM_ERRATA_430973
638 This option enables the workaround for the 430973 Cortex-A8
641 same virtual address, whether due to self-modifying code or virtual
642 to physical address re-mapping, Cortex-A8 does not recover from the
643 stale interworking branch prediction. This results in Cortex-A8
648 available in non-secure mode.
650 config ARM_ERRATA_458693
655 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
662 register may not be available in non-secure mode and thus is not
664 bootloader instead.
666 config ARM_ERRATA_460075
671 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
675 workaround disables the write-allocate mode for the L2 cache via the
677 may not be available in non-secure mode and thus is not available on
678 a multiplatform kernel. This should be applied by the bootloader
681 config ARM_ERRATA_742230
686 This option enables the workaround for the 742230 Cortex-A9
690 the diagnostic register of the Cortex-A9 which causes the DMB
693 register may not be available in non-secure mode and thus is not
695 bootloader instead.
697 config ARM_ERRATA_742231
702 This option enables the workaround for the 742231 Cortex-A9
704 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
709 register of the Cortex-A9 which reduces the linefill issuing
711 diagnostics register may not be available in non-secure mode and thus
713 the bootloader instead.
715 config ARM_ERRATA_643719
720 This option enables the workaround for the 643719 Cortex-A9 (prior to
726 config ARM_ERRATA_720789
730 This option enables the workaround for the 720789 Cortex-A9 (prior to
738 config ARM_ERRATA_743622
743 This option enables the workaround for the 743622 Cortex-A9
745 optimisation in the Cortex-A9 Store Buffer may lead to data
747 register of the Cortex-A9 which disables the Store Buffer
751 may not be available in non-secure mode and thus is not available on a
752 multiplatform kernel. This should be applied by the bootloader instead.
754 config ARM_ERRATA_751472
759 This option enables the workaround for the 751472 Cortex-A9 (prior
765 not be available in non-secure mode and thus is not available on
766 a multiplatform kernel. This should be applied by the bootloader
769 config ARM_ERRATA_754322
773 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
776 can populate the micro-TLB with a stale entry which may be hit with
780 config ARM_ERRATA_754327
784 This option enables the workaround for the 754327 Cortex-A9 (prior to
791 config ARM_ERRATA_364296
792 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
797 hit-under-miss enabled). It sets the undocumented bit 31 in
799 register, thus disabling hit-under-miss without putting the
803 config ARM_ERRATA_764369
808 affecting Cortex-A9 MPCore with two or more processors (all
817 config ARM_ERRATA_764319
821 This option enables the workaround for the 764319 Cortex A-9 erratum.
828 config ARM_ERRATA_775420
832 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
838 config ARM_ERRATA_798181
839 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
842 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
848 config ARM_ERRATA_773022
852 This option enables the workaround for the 773022 Cortex-A15
857 config ARM_ERRATA_818325_852422
862 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
864 - Cortex-A12 852422: Execution of a sequence of instructions might
866 any Cortex-A12 cores yet.
871 config ARM_ERRATA_821420
875 This option enables the workaround for the 821420 Cortex-A12
879 deadlock when the VMOV instructions are issued out-of-order.
881 config ARM_ERRATA_825619
885 This option enables the workaround for the 825619 Cortex-A12
888 and Device/Strongly-Ordered loads and stores might cause deadlock
890 config ARM_ERRATA_857271
894 This option enables the workaround for the 857271 Cortex-A12
898 config ARM_ERRATA_852421
902 This option enables the workaround for the 852421 Cortex-A17
907 config ARM_ERRATA_852423
912 - Cortex-A17 852423: Execution of a sequence of instructions might
914 any Cortex-A17 cores yet.
915 This is identical to Cortex-A12 erratum 852422. It is a separate
916 config option from the A12 erratum due to the way errata are checked
919 config ARM_ERRATA_857272
923 This option enables the workaround for the 857272 Cortex-A17 erratum.
925 This is identical to Cortex-A12 erratum 857271. It is a separate
926 config option from the A12 erratum due to the way errata are checked
935 config ISA
945 config ISA_DMA_API
948 config ARM_ERRATA_814220
957 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
964 config HAVE_SMP
967 This option should be selected by machines which have an SMP-
970 The only effect of this option is to make the SMP-related
973 config SMP
974 bool "Symmetric Multi-Processing"
984 If you say N here, the kernel will run on uni- and multiprocessor
990 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
991 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
992 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
996 config SMP_ON_UP
1001 SMP kernels contain instructions which fail on non-SMP processors.
1009 config CURRENT_POINTER_IN_TPIDRURO
1013 config IRQSTACKS
1018 config ARM_CPU_TOPOLOGY
1027 config SCHED_MC
1028 bool "Multi-core scheduler support"
1031 Multi-core scheduler support improves the CPU scheduler's decision
1032 making when dealing with multi-core CPU chips at a cost of slightly
1035 config SCHED_SMT
1043 config HAVE_ARM_SCU
1048 config HAVE_ARM_ARCH_TIMER
1055 config HAVE_ARM_TWD
1060 config MCPM
1061 bool "Multi-Cluster Power Management"
1065 for (multi-)cluster based systems, such as big.LITTLE based
1068 config MCPM_QUAD_CLUSTER
1077 config BIG_LITTLE
1085 config BL_SWITCHER
1094 config BL_SWITCHER_DUMMY_IF
1112 config VMSPLIT_3G
1114 config VMSPLIT_3G_OPT
1117 config VMSPLIT_2G
1119 config VMSPLIT_1G
1123 config PAGE_OFFSET
1131 config KASAN_SHADOW_OFFSET
1140 config NR_CPUS
1141 int "Maximum number of CPUs (2-32)"
1149 debugging is enabled, which uses half of the per-CPU fixmap
1152 config HOTPLUG_CPU
1153 bool "Support for hot-pluggable CPUs"
1160 config ARM_PSCI
1166 implementing the PSCI specification for CPU-centric power
1171 config HZ_FIXED
1180 config HZ_100
1183 config HZ_200
1186 config HZ_250
1189 config HZ_300
1192 config HZ_500
1195 config HZ_1000
1200 config HZ
1210 config SCHED_HRTICK
1213 config THUMB2_KERNEL
1214 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1220 Thumb-2 mode.
1224 config ARM_PATCH_IDIV
1242 config AEABI
1259 config OABI_COMPAT
1280 config ARCH_SELECT_MEMORY_MODEL
1283 config ARCH_FLATMEM_ENABLE
1286 config ARCH_SPARSEMEM_ENABLE
1290 config HIGHMEM
1309 config HIGHPTE
1310 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1318 user-space 2nd level page tables to reside in high memory.
1320 config CPU_SW_DOMAIN_PAN
1321 bool "Enable use of CPU domains to implement privileged no-access"
1327 use-after-free bugs becoming an exploitable privilege escalation
1331 CPUs with low-vector mappings use a best-efforts implementation.
1335 config HW_PERF_EVENTS
1339 config ARM_MODULE_PLTS
1354 Disabling this is usually safe for small single-platform
1357 config ARCH_FORCE_MAX_ORDER
1372 config ALIGNMENT_TRAP
1378 address divisible by 4. On 32-bit ARM processors, these non-aligned
1381 correct operation of some network protocols. With an IP-only
1384 config UACCESS_WITH_MEMCPY
1390 cores where a 8-word STM instruction give significantly higher
1397 However, if the CPU data cache is using a write-allocate mode,
1400 config PARAVIRT
1407 config PARAVIRT_TIME_ACCOUNTING
1418 config XEN_DOM0
1422 config XEN
1436 config CC_HAVE_STACKPROTECTOR_TLS
1437 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1439 config STACKPROTECTOR_PER_TASK
1459 config USE_OF
1466 config ARCH_WANT_FLAT_DTB_INSTALL
1469 config ATAGS
1478 config DEPRECATED_PARAM_STRUCT
1486 # TEXT and BSS so we preserve their values in the config files.
1487 config ZBOOT_ROM_TEXT
1491 The physical address at which the ROM-able zImage is to be
1493 ROM-able zImage formats normally set this to a suitable
1498 config ZBOOT_ROM_BSS
1503 for the ROM-able zImage which must be available while the
1506 Platforms which normally make use of ROM-able zImage formats
1511 config ZBOOT_ROM
1519 config ARM_APPENDED_DTB
1528 systems with a bootloader that can't be upgraded to accommodate
1536 location into r2 of a bootloader provided DTB is always preferable
1539 config ARM_ATAG_DTB_COMPAT
1546 provided by the bootloader and can't always be stored in a static
1555 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1556 bool "Use bootloader kernel arguments if available"
1558 Uses the command-line options passed by the boot loader instead of
1562 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1563 bool "Extend with bootloader kernel arguments"
1565 The command-line arguments provided by the boot loader will be
1570 config CMDLINE
1576 architectures, you should supply some command-line options at build
1584 config CMDLINE_FROM_BOOTLOADER
1585 bool "Use bootloader kernel arguments if available"
1587 Uses the command-line options passed by the boot loader. If
1591 config CMDLINE_EXTEND
1592 bool "Extend bootloader kernel arguments"
1594 The command-line arguments provided by the boot loader will be
1597 config CMDLINE_FORCE
1603 command-line options your boot loader passes to the kernel.
1606 config XIP_KERNEL
1607 bool "Kernel Execute-In-Place from ROM"
1611 Execute-In-Place allows the kernel to run from non-volatile storage
1614 to RAM. Read-write sections, such as the data section and stack,
1628 config XIP_PHYS_ADDR
1637 config XIP_DEFLATED_DATA
1648 config ARCH_SUPPORTS_KEXEC
1651 config ATAGS_PROC
1659 config ARCH_SUPPORTS_CRASH_DUMP
1662 config AUTO_ZRELADDR
1668 will be determined at run-time, either by masking the current IP
1673 config EFI_STUB
1676 config EFI
1686 by UEFI firmware (such as non-volatile variables, realtime
1692 config DMI
1701 continue to boot on existing non-UEFI platforms.
1707 to be enabled much earlier than we do on ARM, which is non-trivial.
1723 config FPE_NWFPE
1730 your machine has an FPA or floating point co-processor podule.
1735 config FPE_NWFPE_XP
1739 Say Y to include 80-bit support in the kernel floating-point
1740 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1741 Note that gcc does not generate 80-bit operations by default,
1747 config FPE_FASTFPE
1754 It is very simple, and approximately 3-6 times faster than NWFPE.
1761 config VFP
1762 bool "VFP-format floating point maths"
1768 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1773 config VFPv3
1778 config NEON
1785 config KERNEL_MODE_NEON
1797 config ARCH_SUSPEND_POSSIBLE
1802 config ARM_CPU_SUSPEND
1806 config ARCH_HIBERNATION_POSSIBLE