16 #include <asm/mmu.h>
87 	 * If Not already present get a free slot from MMU.  in tlb_entry_insert()
99 	 * Commit the Entry to MMU  in tlb_entry_insert()
131  * Un-conditionally (without lookup) erase the entire MMU contents
136 	struct cpuinfo_arc_mmu *mmu = &mmuinfo;  in local_flush_tlb_all()  local
139 	int num_tlb = mmu->sets * mmu->ways;  in local_flush_tlb_all()
182 	 * Only for fork( ) do we need to move parent to a new MMU ctxt,  in local_flush_tlb_mm()
245 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
274  * Delete TLB entry in MMU for a given page (??? address)
403 	 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)  in create_tlb()
407 	 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.  in create_tlb()
443 	 * ARC MMU provides fully orthogonal access bits for K/U mode,  in create_tlb()
445 	 * Here we convert 3 PTE bits into 6 MMU bits:  in create_tlb()
465  *  -pre-install the corresponding TLB entry into MMU
525  *  - MMU page size (typical 8K, RTL fixed)
571 	struct cpuinfo_arc_mmu *mmu = &mmuinfo;  in arc_mmu_mumbojumbo()  local
579 	mmu->ver = (bcr >> 24);  in arc_mmu_mumbojumbo()
581 	if (is_isa_arcompact() && mmu->ver == 3) {  in arc_mmu_mumbojumbo()
583 		mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);  in arc_mmu_mumbojumbo()
584 		mmu->sets = 1 << mmu3->sets;  in arc_mmu_mumbojumbo()
585 		mmu->ways = 1 << mmu3->ways;  in arc_mmu_mumbojumbo()
591 		mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);  in arc_mmu_mumbojumbo()
592 		mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);  in arc_mmu_mumbojumbo()
593 		mmu->sets = 64 << mmu4->n_entry;  in arc_mmu_mumbojumbo()
594 		mmu->ways = mmu4->n_ways * 2;  in arc_mmu_mumbojumbo()
598 		mmu->pae = mmu4->pae;  in arc_mmu_mumbojumbo()
601 	if (mmu->s_pg_sz_m)  in arc_mmu_mumbojumbo()
603 			  mmu->s_pg_sz_m,  in arc_mmu_mumbojumbo()
607 		      "MMU [v%x]\t: %dk%s, swalk %d lvl, JTLB %dx%d, uDTLB %d, uITLB %d%s%s%s\n",  in arc_mmu_mumbojumbo()
608 		       mmu->ver, mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS,  in arc_mmu_mumbojumbo()
609 		       mmu->sets, mmu->ways,  in arc_mmu_mumbojumbo()
612 		       IS_AVAIL2(mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));  in arc_mmu_mumbojumbo()
624 	struct cpuinfo_arc_mmu *mmu = &mmuinfo;  in arc_mmu_init()  local
639 	 * Ensure that MMU features assumed by kernel exist in hardware.  in arc_mmu_init()
644 	if (is_isa_arcompact() && mmu->ver == 3)  in arc_mmu_init()
646 	else if (is_isa_arcv2() && mmu->ver >= 4)  in arc_mmu_init()
650 		panic("MMU ver %d doesn't match kernel built for\n", mmu->ver);  in arc_mmu_init()
652 	if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))  in arc_mmu_init()
653 		panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));  in arc_mmu_init()
656 	    mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))  in arc_mmu_init()
657 		panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",  in arc_mmu_init()
660 	if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)  in arc_mmu_init()
663 	/* Enable the MMU with ASID 0 */  in arc_mmu_init()
666 	/* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */  in arc_mmu_init()
685  * MMU cmd getIndex(vaddr) abstracts that out.
688 #define SET_WAY_TO_IDX(mmu, set, way)  ((set) * mmu->ways + (way))  argument
690 /* Handling of Duplicate PD (TLB entry) in MMU.
692  * -MMU complaints not at the time of duplicate PD installation, but at the
703 	struct cpuinfo_arc_mmu *mmu = &mmuinfo;  in do_tlb_overlap_fault()  local
705 	int set, n_ways = mmu->ways;  in do_tlb_overlap_fault()
708 	BUG_ON(mmu->ways > 4);  in do_tlb_overlap_fault()
713 	for (set = 0; set < mmu->sets; set++) {  in do_tlb_overlap_fault()
721 					  SET_WAY_TO_IDX(mmu, set, way));  in do_tlb_overlap_fault()
754 						SET_WAY_TO_IDX(mmu, set, way));  in do_tlb_overlap_fault()