Lines Matching refs:PTP
409 a HW PTP clock source, to allow time conversion in userspace and
410 optionally synchronize system time with a userspace PTP stack such
411 as linuxptp. For the PTP clock API, see Documentation/driver-api/ptp.rst.
568 /* PTP v1, UDP, any kind of event packet */
624 3.2 Special considerations for stacked PTP Hardware Clocks
627 There are situations when there may be more than one PHC (PTP Hardware Clock)
644 When a DSA switch is attached to a host port, PTP synchronization has to
646 jitter between the host port and its PTP partner. For this reason, some DSA
655 By design, PTP timestamping with a DSA switch does not need any special
657 host port also supports PTP timestamping, DSA will take care of intercepting
663 In the generic layer, DSA provides the following infrastructure for PTP
675 PTP TX timestamp register (or sometimes a FIFO) where the timestamp
677 key-value pairs of PTP sequence ID/message type/domain number and the
681 the PTP transport type, and ``ptp_parse_header`` to interpret the PTP
686 no follow-up message required by the PTP protocol (because the
692 identify PTP event messages (any other packets, including PTP general
708 switches do. However, PHYs may be able to detect and timestamp PTP packets, for
712 A PHY driver that supports PTP timestamping must create a ``struct
766 trigger before the existence of stacked PTP clocks. One example has to do with
779 1. "TX": checks whether PTP timestamping has been previously enabled through
800 that PTP timestamping is not enabled for anything other than the outermost PHC,