powerpc/fsl/dcsr.txt

2 Debug Control and Status Register (DCSR) Binding
11 Debug Control and Status Register Memory Map
166 CoreNet Debug Controller
169 the CoreNet Debug controller.
184 	The CoreNet Debug controller occupies two regions in the DCSR space
187 	The first register range describes the CoreNet Debug Controller
190 	The second register range describes the CoreNet Debug Controller
200 Data Path Debug controller
203 the DPAA Debug Controller. This controller controls debug configuration
212 	or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
229 OCeaN Debug controller
232 the OCN Debug Controller.
240 	or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
257 DDR Controller Debug controller
260 the OCN Debug Controller.
300 	or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
321 the RCPM Debug Controller. This functionlity is limited to the
330 	or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the