mpc85xx: rename sdram_init() lbc_sdram_init()

sdram_init() is used to initialize sdram on the lbc. Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kum

mpc85xx: rename sdram_init() lbc_sdram_init()

sdram_init() is used to initialize sdram on the lbc. Rename it
accordingly.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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mpc85xx boards: initdram() cleanup/bugfix

Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I

mpc85xx boards: initdram() cleanup/bugfix

Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured

Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().

powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured

Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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fsl: Clean up printing of PCI boot info

Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the

fsl: Clean up printing of PCI boot info

Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:

...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org

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Merge branch 'master' of /home/wd/git/u-boot/master

Merge branch 'master' of /home/wd/git/u-boot/custodians

powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases

Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat

powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases

Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.

Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

83xx/85xx/86xx: LBC register cleanup

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.

To do th

83xx/85xx/86xx: LBC register cleanup

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:

cpu/arm_cortexa8/s5pc1xx/cache.c
include/asm-arm/arch-s5pc1xx/sys_proto.h
include/sja1000.h

Signed-off-by: Minkyu Kang <mk7.kang

Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:

cpu/arm_cortexa8/s5pc1xx/cache.c
include/asm-arm/arch-s5pc1xx/sys_proto.h
include/sja1000.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Merge branch 'master' into next

Merge branch 'master' of git://git.denx.de/u-boot-arm

Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"

This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.

There isn't any need to modify the API for fsl_pci_init_port to pass the
s

Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"

This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.

There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status. We can determine that
internally to fsl_pci_init_port. Revert the patch that makes the API
change.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

ppc/85xx/pci: fsl_pci_init: pcie agent mode support

Originally written by Jason Jin and Mingkai Hu for mpc8536.

When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI

ppc/85xx/pci: fsl_pci_init: pcie agent mode support

Originally written by Jason Jin and Mingkai Hu for mpc8536.

When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0

* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: update PCI/PCI-e support code

The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile.

sbc8548: update PCI/PCI-e support code

The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.

It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.

Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: correct local bus SDRAM size from 64M to 128M

The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was

sbc8548: correct local bus SDRAM size from 64M to 128M

The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: use I/O accessors

Sweep throught the board specific file and replace the various
register proddings with the equivalent I/O accessors.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriv

sbc8548: use I/O accessors

Sweep throught the board specific file and replace the various
register proddings with the equivalent I/O accessors.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: remove eTSEC3/4 voltage hack

With only eTSEC1 and 2 being brought out to RJ-45 connectors, we
aren't interested in the eTSEC3/4 voltage hack on this board

Signed-off-by: Paul Gortmaker <pa

sbc8548: remove eTSEC3/4 voltage hack

With only eTSEC1 and 2 being brought out to RJ-45 connectors, we
aren't interested in the eTSEC3/4 voltage hack on this board

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: get_clock_freq is not valid for this board

The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms. It would
be nice if we co

sbc8548: get_clock_freq is not valid for this board

The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms. It would
be nice if we could read the 33 vs. 66MHz status somehow, but in
the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other
non-CDS boards do.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: delete unused MPC8548CDS info carried over from port

There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
t

sbc8548: delete unused MPC8548CDS info carried over from port

There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.

Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot. That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.

Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: enable use of PCI network cards

Create a board_eth_init to allow a place to hook in
the PCI ethernet init after all the eTSEC are up
and configured.

Signed-off-by: Paul Gortmaker <paul.gor

sbc8548: enable use of PCI network cards

Create a board_eth_init to allow a place to hook in
the PCI ethernet init after all the eTSEC are up
and configured.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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sbc8548: replace README with completely new document

The previous README.sbc8548 was pretty much content-free. Replace
it with something that actually gives the end user some relevant
hardware detai

sbc8548: replace README with completely new document

The previous README.sbc8548 was pretty much content-free. Replace
it with something that actually gives the end user some relevant
hardware details, and also lists the u-boot configuration choices.

Also in the cosmetic department, fix the bogus line in the Makefile
that was carried over from the SBC8560 Makefile, and the typo in
the sbc8548.c copyright.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host

Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-

ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host

Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.

Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

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Merge branch 'master' of /home/wd/git/u-boot/custodians