tcg: Remove movi and dupi opcodes

These are now completely covered by mov from a
TYPE_CONST temporary.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar

tcg: Remove movi and dupi opcodes

These are now completely covered by mov from a
TYPE_CONST temporary.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Convert tcg_gen_dupi_vec to TCG_CONST

Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hos

tcg: Convert tcg_gen_dupi_vec to TCG_CONST

Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hosts.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging

Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.

# gpg: Signa

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging

Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.

# gpg: Signature made Thu 08 Oct 2020 13:55:22 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20201008:
accel/tcg: Fix computing of is_write for MIPS
tcg: Remove TCG_TARGET_HAS_cmp_vec
tcg/optimize: Fold dup2_vec
tcg: Fix generation of dupi_vec for 32-bit host
tcg/i386: Fix dupi for avx2 32-bit hosts
tcg: Remove TCGOpDef.used
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
tcg: Remove TCG_CT_REG
tcg: Move sorted_args into TCGArgConstraint.sort_index
tcg: Drop union from TCGArgConstraint
tcg: Adjust simd_desc size encoding

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Fix generation of dupi_vec for 32-bit host

The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits. It does
not work to use this for a uint

tcg: Fix generation of dupi_vec for 32-bit host

The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits. It does
not work to use this for a uint64_t value that happens to be
small enough to fit in tcg_target_ulong.

Fixes: d2fd745fe8b
Fixes: db432672dc5
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200717' into staging

Fix vector min/max fallback expansion
Fix singlestep from exception and interrupt

# gpg: Signature made Fri 17 Jul 202

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200717' into staging

Fix vector min/max fallback expansion
Fix singlestep from exception and interrupt

# gpg: Signature made Fri 17 Jul 2020 19:13:32 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20200717:
tcg/cpu-exec: precise single-stepping after an interrupt
tcg/cpu-exec: precise single-stepping after an exception
tcg: Save/restore vecop_list around minmax fallback

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Save/restore vecop_list around minmax fallback

Forgetting this asserts when tcg_gen_cmp_vec is called from
within tcg_gen_cmpsel_vec.

Fixes: 72b4c792c7a
Signed-off-by: Richard Henderson <richa

tcg: Save/restore vecop_list around minmax fallback

Forgetting this asserts when tcg_gen_cmp_vec is called from
within tcg_gen_cmpsel_vec.

Fixes: 72b4c792c7a
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging

Vector rotate support
Signal handling support for NetBSD arm/aarch64

# gpg: Signature made Tue 02 Jun 2020 17:43:05 BS

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging

Vector rotate support
Signal handling support for NetBSD arm/aarch64

# gpg: Signature made Tue 02 Jun 2020 17:43:05 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20200602:
accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler
accel/tcg: Adjust cpu_signal_handler for NetBSD/arm
tcg: Improve move ops in liveness_pass_2
target/s390x: Use tcg_gen_gvec_rotl{i,s,v}
target/ppc: Use tcg_gen_gvec_rotlv
tcg/ppc: Implement INDEX_op_rot[lr]v_vec
tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec
tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec
tcg: Implement gvec support for rotate by scalar
tcg: Remove expansion to shift by vector from do_shifts
tcg: Implement gvec support for rotate by vector
tcg: Implement gvec support for rotate by immediate

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Implement gvec support for rotate by scalar

No host backend support yet, but the interfaces for rotls
are in place. Only implement left-rotate for now, as the
only known use of vector rotate b

tcg: Implement gvec support for rotate by scalar

No host backend support yet, but the interfaces for rotls
are in place. Only implement left-rotate for now, as the
only known use of vector rotate by scalar is s390x, so any
right-rotate would be unused and untestable.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Remove expansion to shift by vector from do_shifts

We do not reflect this expansion in tcg_can_emit_vecop_list,
so it is unused and unusable. However, we actually perform
the same expansion in

tcg: Remove expansion to shift by vector from do_shifts

We do not reflect this expansion in tcg_can_emit_vecop_list,
so it is unused and unusable. However, we actually perform
the same expansion in do_gvec_shifts, so it is also unneeded.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Implement gvec support for rotate by vector

No host backend support yet, but the interfaces for rotlv
and rotrv are in place.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: R

tcg: Implement gvec support for rotate by vector

No host backend support yet, but the interfaces for rotlv
and rotrv are in place.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Drop the generic expansion from rot to shift; we can do better
for each backend, and then this code becomes unused.

show more ...

tcg: Implement gvec support for rotate by immediate

No host backend support yet, but the interfaces for rotli
are in place. Canonicalize immediate rotate to the left,
based on a survey of architect

tcg: Implement gvec support for rotate by immediate

No host backend support yet, but the interfaces for rotli
are in place. Canonicalize immediate rotate to the left,
based on a survey of architectures, but provide both left
and right shift interfaces to the translators.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging

Add cpu_{ld,st}*_mmuidx_ra
Remove MMU_MODE*_SUFFIX
Move tcg headers under include/

# gpg: Signature made Thu 16 Jan 20

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging

Add cpu_{ld,st}*_mmuidx_ra
Remove MMU_MODE*_SUFFIX
Move tcg headers under include/

# gpg: Signature made Thu 16 Jan 2020 01:36:41 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20200115: (34 commits)
MAINTAINERS: Replace Claudio Fontana for tcg/aarch64
configure: Remove tcg/ from the preprocessor include search list
tcg: Move TCG headers to include/tcg/
tcg: Search includes in the parent source directory
tcg: Search includes from the project root source directory
cputlb: Expand cpu_ldst_template.h in cputlb.c
cputlb: Remove support for MMU_MODE*_SUFFIX
target/ppc: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
target/s390x: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0,1}_SUFFIX
target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX
target/unicore32: Remove MMU_MODE{0,1}_SUFFIX
target/sh4: Remove MMU_MODE{0,1}_SUFFIX
target/microblaze: Remove MMU_MODE{0,1,2}_SUFFIX
target/i386: Remove MMU_MODE{0,1,2}_SUFFIX
target/cris: Remove MMU_MODE{0,1}_SUFFIX
target/alpha: Remove MMU_MODE{0,1}_SUFFIX
target/nios2: Remove MMU_MODE{0,1}_SUFFIX
cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Search includes from the project root source directory

We currently search both the root and the tcg/ directories for tcg
files:

$ git grep '#include "tcg/' | wc -l
28

$ git grep '#incl

tcg: Search includes from the project root source directory

We currently search both the root and the tcg/ directories for tcg
files:

$ git grep '#include "tcg/' | wc -l
28

$ git grep '#include "tcg[^/]' | wc -l
94

To simplify the preprocessor search path, unify by expliciting the
tcg/ directory.

Patch created mechanically by running:

$ for x in \
tcg.h tcg-mo.h tcg-op.h tcg-opc.h \
tcg-op-gvec.h tcg-gvec-desc.h; do \
sed -i "s,#include \"$x\",#include \"tcg/$x\"," \
$(git grep -l "#include \"$x\""); \
done

Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts)
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200101112303.20724-2-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190709' into staging

Minor gvec fix for as-yet uncommitted altivec host.
Build fix for riscv host.

# gpg: Signature made Tue 09 Jul 2019 07

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190709' into staging

Minor gvec fix for as-yet uncommitted altivec host.
Build fix for riscv host.

# gpg: Signature made Tue 09 Jul 2019 07:27:34 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190709:
tcg: Fix expansion of INDEX_op_not_vec
tcg/riscv: Fix RISC-VH host build failure

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Fix expansion of INDEX_op_not_vec

This operation can always be emitted, even if we need to
fall back to xor. Adjust the assertions to match.

Signed-off-by: Richard Henderson <richard.henderso

tcg: Fix expansion of INDEX_op_not_vec

This operation can always be emitted, even if we need to
fall back to xor. Adjust the assertions to match.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2019-06-11-v3' into staging

Miscellaneous patches for 2019-06-11

# gpg: Signature made Wed 12 Jun 2019 12:20:41 BST
# gpg:

Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2019-06-11-v3' into staging

Miscellaneous patches for 2019-06-11

# gpg: Signature made Wed 12 Jun 2019 12:20:41 BST
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-misc-2019-06-11-v3:
MAINTAINERS: Polish headline decorations
MAINTAINERS: Improve section headlines
MAINTAINERS: Remove duplicate entries of qemu-devel@nongnu.org
Clean up a header guard symbols (again)
Supply missing header guards
Clean up a few header guard symbols
scripts/clean-header-guards: Fix handling of trailing comments
Normalize position of header guard
Include qemu-common.h exactly where needed
Include qemu/module.h where needed, drop it from qemu-common.h
qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h
qemu-common: Move tcg_enabled() etc. to sysemu/tcg.h

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Include qemu-common.h exactly where needed

No header includes qemu-common.h after this commit, as prescribed by
qemu-common.h's file comment.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Me

Include qemu-common.h exactly where needed

No header includes qemu-common.h after this commit, as prescribed by
qemu-common.h's file comment.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190523143508.25387-5-armbru@redhat.com>
[Rebased with conflicts resolved automatically, except for
include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c
block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c
target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h
target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h
target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h
target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and
net/tap-bsd.c fixed up]

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190522' into staging

Misc gvec improvements

# gpg: Signature made Wed 22 May 2019 23:25:48 BST
# gpg: using RSA key 7A481E78

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190522' into staging

Misc gvec improvements

# gpg: Signature made Wed 22 May 2019 23:25:48 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190522:
tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store
tcg/aarch64: Allow immediates for vector ORR and BIC
tcg/aarch64: Build vector immediates with two insns
tcg/aarch64: Use MVNI in tcg_out_dupi_vec
tcg/aarch64: Split up is_fimm
tcg/aarch64: Support vector bitwise select value
tcg/i386: Use umin/umax in expanding unsigned compare
tcg/i386: Remove expansion for missing minmax
tcg/i386: Support vector comparison select value
tcg: Add TCG_OPF_NOT_PRESENT if TCG_TARGET_HAS_foo is negative
tcg: Expand vector minmax using cmp+cmpsel
tcg: Introduce do_op3_nofail for vector expansion
tcg: Add support for vector compare select
tcg: Add support for vector bitwise select
tcg: Fix missing checks and clears in tcg_gen_gvec_dup_mem
tcg/i386: Fix dupi/dupm for avx1 and 32-bit hosts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Expand vector minmax using cmp+cmpsel

Provide a generic fallback for the min/max operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

tcg: Introduce do_op3_nofail for vector expansion

This makes do_op3 match do_op2 in allowing for failure,
and thus fall back expansions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.o

tcg: Introduce do_op3_nofail for vector expansion

This makes do_op3 match do_op2 in allowing for failure,
and thus fall back expansions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Add support for vector compare select

Perform a per-element conditional move. This combination operation is
easier to implement on some host vector units than plain cmp+bitsel.
Omit the usual

tcg: Add support for vector compare select

Perform a per-element conditional move. This combination operation is
easier to implement on some host vector units than plain cmp+bitsel.
Omit the usual gvec interface, as this is intended to be used by
target-specific gvec expansion call-backs.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

tcg: Add support for vector bitwise select

This operation performs d = (b & a) | (c & ~a), and is present
on a majority of host vector units. Include gvec expanders.

Signed-off-by: Richard Henders

tcg: Add support for vector bitwise select

This operation performs d = (b & a) | (c & ~a), and is present
on a majority of host vector units. Include gvec expanders.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190513' into staging

Improve code generation for vector duplication.
Add vector expansions for shifts by non-constant scalar.
Add vector exp

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190513' into staging

Improve code generation for vector duplication.
Add vector expansions for shifts by non-constant scalar.
Add vector expansions for shifts by vector.
Add integer and vector expansions for absolute value.
Several patches in preparation for Altivec.
Bug fix for tcg/aarch64 vs min/max.

# gpg: Signature made Tue 14 May 2019 00:58:02 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190513: (31 commits)
tcg/aarch64: Do not advertise minmax for MO_64
target/xtensa: Use tcg_gen_abs_i32
target/tricore: Use tcg_gen_abs_tl
target/s390x: Use tcg_gen_abs_i64
target/ppc: Use tcg_gen_abs_tl
target/ppc: Use tcg_gen_abs_i32
target/cris: Use tcg_gen_abs_tl
target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
tcg/aarch64: Support vector absolute value
tcg/i386: Support vector absolute value
tcg: Add support for vector absolute value
tcg: Add support for integer absolute value
tcg/i386: Support vector scalar shift opcodes
tcg: Add gvec expanders for vector shift by scalar
tcg/aarch64: Support vector variable shift opcodes
tcg/i386: Support vector variable shift opcodes
tcg: Add gvec expanders for variable shift
tcg: Add INDEX_op_dupm_vec
tcg/aarch64: Implement tcg_out_dupm_vec
tcg/i386: Implement tcg_out_dupm_vec
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tcg: Add support for vector absolute value

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

tcg: Add gvec expanders for vector shift by scalar

Allow expansion either via shift by scalar or by replicating
the scalar for shift by vector.

Signed-off-by: Richard Henderson <richard.henderson@l

tcg: Add gvec expanders for vector shift by scalar

Allow expansion either via shift by scalar or by replicating
the scalar for shift by vector.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Use a private structure for do_gvec_shifts.

show more ...