| 091d5677 | 12-Sep-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-arm: Improve GUEST_BASE qemu_ld/st
If we pull the code to emit the actual load/store into a subroutine,
we can share the reg+reg addressing mode code between softmmu and
usermode. This lets us
tcg-arm: Improve GUEST_BASE qemu_ld/st
If we pull the code to emit the actual load/store into a subroutine,
we can share the reg+reg addressing mode code between softmmu and
usermode. This lets us load GUEST_BASE into a temporary register
rather than attempting to add it piece-wise to the address.
Which lets us use movw+movt for armv7, rather than (up to) 4 adds.
Code size for pre-armv7 stays the same.
Signed-off-by: Richard Henderson <rth@twiddle.net>
show more ...
|
| ee06e230 | 30-Aug-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-arm: Move the tlb addend load earlier
There are free scheduling slots between the sequence of
comparison instructions. This requires changing the
register in use to avoid conflict with those co
tcg-arm: Move the tlb addend load earlier
There are free scheduling slots between the sequence of
comparison instructions. This requires changing the
register in use to avoid conflict with those compares.
Signed-off-by: Richard Henderson <rth@twiddle.net>
show more ...
|
| 66c2056f | 30-Aug-2013 |
Richard Henderson <rth@twiddle.net> |
tcg-arm: Remove restriction on qemu_ld output register
The main intent of the patch is to allow the tlb addend register
to be changed, without tying that change to the constraint. But
the most comm
tcg-arm: Remove restriction on qemu_ld output register
The main intent of the patch is to allow the tlb addend register
to be changed, without tying that change to the constraint. But
the most common side-effect seems to be to enable usage of ldrd
with the r0,r1 pair.
Signed-off-by: Richard Henderson <rth@twiddle.net>
show more ...
|