| #
3590f01e |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Split cexc and ftt from env->fsr
These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.
Signed-off-by: Richard Henderson <richar
target/sparc: Split cexc and ftt from env->fsr
These two fields are adjusted by all FPop insns.
Having them separate makes it easier to set without masking.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-20-richard.henderson@linaro.org>
show more ...
|
| #
db713911 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge check_ieee_exceptions with FPop helpers
If an exception is to be raised, the destination fp register
should be unmodified. The current implementation is incorrect,
in that doubl
target/sparc: Merge check_ieee_exceptions with FPop helpers
If an exception is to be raised, the destination fp register
should be unmodified. The current implementation is incorrect,
in that double results will be written back before calling
gen_helper_check_ieee_exceptions, despite the placement of
gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[].
We can simplify the entire implementation by having each
FPOp helper call check_ieee_exceptions. For the moment this
requires that all FPop helpers write to the TCG global cpu_fsr,
so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-19-richard.henderson@linaro.org>
show more ...
|
| #
1ccd6e13 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <
target/sparc: Introduce cpu_get_fsr, cpu_put_fsr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-16-richard.henderson@linaro.org>
show more ...
|
| #
ba21dc99 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for Fdmulq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ay
target/sparc: Use i128 for Fdmulq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>
show more ...
|
| #
fdc50716 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FdTOq, FxTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FdTOq, FxTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-13-richard.henderson@linaro.org>
show more ...
|
| #
0b2a61cc |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FsTOq, FiTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FsTOq, FiTOq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-12-richard.henderson@linaro.org>
show more ...
|
| #
f3ceafad |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FCMPq, FCMPEq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.
target/sparc: Use i128 for FCMPq, FCMPEq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-11-richard.henderson@linaro.org>
show more ...
|
| #
25a5769e |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FqTOd, FqTOx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FqTOd, FqTOx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-10-richard.henderson@linaro.org>
show more ...
|
| #
d81e3efe |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FqTOs, FqTOi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.c
target/sparc: Use i128 for FqTOs, FqTOi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org>
show more ...
|
| #
16bedf89 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-
target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-8-richard.henderson@linaro.org>
show more ...
|
| #
e41716be |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use i128 for FSQRTq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ay
target/sparc: Use i128 for FSQRTq
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-7-richard.henderson@linaro.org>
show more ...
|
| #
daf457d4 |
| 03-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Inline FNEG, FABS
These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
R
target/sparc: Inline FNEG, FABS
These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>
show more ...
|
| #
3e01f114 |
| 05-Nov-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging
target/sparc: Explicitly compute condition codes
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN8
Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging
target/sparc: Explicitly compute condition codes
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVH9oodHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/M8QgAgPTp/wFLVnSRFLaN
# fBoelVhM4WTWMQ+SUwZMtCvqcMHaBxIMu+hyk5MI11hFOUi9N+vWvRb+NZ6JbK+1
# sqWcx0NdYfNdOeoi1dgzGgcCkFA8u9zW/K7Ih0W8WuU20uiJ4Zw/qmnEELIl/mZR
# 5Ft1mhLMhQSYsH0KSypugLWBxR9SFNH1cV3C1SG2q+6snm/mhKk9NN18zJGFdmmY
# 4CQThx159P/DaPUONZbSAMN94opu6K8FSymELPDUZBYwJRq7fyGKYuDUGRvN1kxx
# I8p/MF1V5Vcth9lvGyBYulFWjo9BDMpkIdmWzXZLOWfzZVAed8PcglxoQqgMbU5u
# eyY/Cw==
# =Tv1h
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Nov 2023 04:09:46 HKT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu: (21 commits)
target/sparc: Check for invalid cond in gen_compare_reg
target/sparc: Implement UDIV inline
target/sparc: Implement UDIVX and SDIVX inline
target/sparc: Discard cpu_cond at the end of each insn
target/sparc: Record entire jump condition in DisasContext
target/sparc: Merge gen_op_next_insn into only caller
target/sparc: Pass displacement to advance_jump_cond
target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond
target/sparc: Merge gen_branch2 into advance_pc
target/sparc: Do flush_cond in advance_jump_cond
target/sparc: Always copy conditions into a new temporary
target/sparc: Change DisasCompare.c2 to int
target/sparc: Remove DisasCompare.is_bool
target/sparc: Remove CC_OP leftovers
target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV
target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB
target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD
target/sparc: Remove CC_OP_DIV
target/sparc: Remove CC_OP_LOGIC
target/sparc: Split psr and xcc into components
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
f3141174 |
| 16-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Implement UDIVX and SDIVX inline
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson
target/sparc: Implement UDIVX and SDIVX inline
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
| #
b597eedc |
| 14-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Remove CC_OP leftovers
All instructions have been converted to generate
full condition codes explicitly.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cav
target/sparc: Remove CC_OP leftovers
All instructions have been converted to generate
full condition codes explicitly.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
| #
13260103 |
| 14-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Remove CC_OP_DIV
Return both result and overflow from helper_[us]div.
Compute all flags explicitly in gen_op_[us]divcc.
Marginally improve the INT64_MIN special case in helper_sdiv.
target/sparc: Remove CC_OP_DIV
Return both result and overflow from helper_[us]div.
Compute all flags explicitly in gen_op_[us]divcc.
Marginally improve the INT64_MIN special case in helper_sdiv.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
| #
c60be6e3 |
| 26-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging
Convert target/sparc to decodetree.
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU5
Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging
Convert target/sparc to decodetree.
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU5ruAdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9NWQgAjkWxZi9Je3yWR0x0
# mQmlx0zlyjK4PeMGS14mr0mxFAqvC5gFHNzw0WtLaVw9gyfm6EKXwervtm9mCg7F
# PPQzF9IqSoKqGV2fFlWpVWmUPmKNhLY5hS7Pvampg8Tkt6X6NJQdbaUpEQW6U47I
# C4/AAygaj6fd99BEZI36A2oxg6D0HM9cV1LUm43e+yQ1KCQaTO+3u8oDZA8MkXu1
# p2bxPXazClLe+ywwtR9tp28IgQszQ10NxECzhJ34ezLCbTreH//ycpPI2h8Xskdc
# lDkCu3OJa8aIalGOpDL71Qemp9KfRYkOyPlahAZx3haZC24fnVvVRoMiV8Z5+iYk
# gq2VnA==
# =/gf2
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 26 Oct 2023 09:12:16 JST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu: (94 commits)
target/sparc: Remove disas_sparc_legacy
target/sparc: Convert FZERO, FONE to decodetree
target/sparc: Move FPACK16, FPACKFIX to decodetree
target/sparc: Move FPCMP* to decodetree
target/sparc: Convert FCMP, FCMPE to decodetree
target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
target/sparc: Move FdTOq, FxTOq to decodetree
target/sparc: Move FiTOq, FsTOq to decodetree
target/sparc: Move FqTOd, FqTOx to decodetree
target/sparc: Move FqTOs, FqTOi to decodetree
target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
target/sparc: Move gen_fop_FD insns to decodetree
target/sparc: Move FDMULQ to decodetree
target/sparc: Move FSMULD to decodetree
target/sparc: Move gen_fop_QQQ insns to decodetree
target/sparc: Move gen_fop_DDD insns to decodetree
target/sparc: Move gen_fop_FFF insns to decodetree
target/sparc: Move FSQRTq to decodetree
target/sparc: Move gen_fop_DD insns to decodetree
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
fafba1bb |
| 10-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Use tcg_gen_vec_{add,sub}*
Replace the local helpers for the same integer operations.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave
target/sparc: Use tcg_gen_vec_{add,sub}*
Replace the local helpers for the same integer operations.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
| #
da681406 |
| 05-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by:
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
| #
186e7890 |
| 16-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/sparc: Implement check_align inline
Emit the exception at the end of the translation block,
so that the non-exception case can fall through.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ila
target/sparc: Implement check_align inline
Emit the exception at the end of the translation block,
so that the non-exception case can fall through.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
|
Revision tags: v8.0.0, v7.2.0, v7.0.0, v6.2.0, v6.1.0, v5.2.0, v5.0.0, v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0, v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, libfdt-20181002, ppc-for-3.1-20180925, ppc-for-3.1-20180907, ppc-for-3.1-20180821, v3.0.0, v3.0.0-rc4, v2.12.1, ppc-for-3.0-20180801, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, ppc-for-3.0-20180716, v3.0.0-rc0, ppc-for-3.0-20180709, ppc-for-3.0-20180703, v2.11.2, ppc-for-3.0-20180622, ppc-for-3.0-20180618, ppc-for-3.0-20180612, ppc-for-2.13-20180504, ppc-for-2.13-20180427, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, ppc-for-2.12-20180410, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, ppc-for-2.12-20180319, ppc-for-2.12-20180315, ppc-for-2.12-20180306, ppc-for-2.12-20180302, ppc-for-2.12-20180216, v2.11.1, ppc-for-2.12-20180212, ppc-for-2.12-20180129, ppc-for-2.12-20180121, ppc-for-2.12-20180119, ppc-for-2.12-20180117, ppc-for-2.12-20180111, ppc-for-2.12-20180108, ppc-for-2.12-20180103, ppc-for-2.12-20171219, v2.10.2, ppc-for-2.12-20171215, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, ppc-for-2.11-20171205, ppc-for-2.11-20171204, v2.11.0-rc3, ppc-for-2.11-20171127, ppc-for-2.11-20171122, v2.11.0-rc2, ppc-for-2.11-20171120, v2.11.0-rc1, ppc-for-2.11-20171114, ppc-for-2.11-20171108, v2.11.0-rc0, ppc-for-2.11-20171017, v2.10.1, ppc-for-2.11-20170927, ppc-for-2.11-20170915, ppc-for-2.11-20170908, v2.9.1, v2.10.0, v2.10.0-rc4, ppc-for-2.10-20170823, ppc-for-2.10-20170822, v2.10.0-rc3, ppc-for-2.10-20170809, v2.10.0-rc2, v2.10.0-rc1, ppc-for-2.10-20170731, v2.10.0-rc0, ppc-for-2.10-20170725, ppc-for-2.10-20170717, ppc-for-2.10-20170714, ppc-for-2.10-20170711, ppc-for-2.10-20170630, ppc-for-2.10-20170609, ppc-for-2.10-20170606, ppc-for-2.10-20170525, ppc-for-2.10-20170511, ppc-for-2.10-20170510, ppc-for-2.10-20170426, ppc-for-2.10-20170424, v2.8.1.1, v2.9.0, v2.9.0-rc5, v2.9.0-rc4, v2.9.0-rc3, ppc-for-2.9-20170403, v2.8.1, ppc-for-2.9-20170329, v2.9.0-rc2, ppc-for-2.9-20170323, v2.9.0-rc1, v2.9.0-rc0, ppc-for-2.9-20170314, ppc-for-2.9-20170306, submodule-update-20170303, ppc-for-2.9-20170303, ppc-for-2.9-20170301, ppc-for-2.9-20170222, isa-cleanup-20170206, ppc-for-2.9-20170202 |
|
| #
0f6bcf68 |
| 19-Jan-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into staging
add OpenSPARC T1 emulation
# gpg: Signature made Wed 18 Jan 2017 22:25:47 GMT
# gpg: using RSA key
Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into staging
add OpenSPARC T1 emulation
# gpg: Signature made Wed 18 Jan 2017 22:25:47 GMT
# gpg: using RSA key 0x3360C3F7411A125F
# gpg: Good signature from "Artyom Tarasenko <atar4qemu@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2AD8 6149 17F4 B2D7 05C0 BB12 3360 C3F7 411A 125F
* remotes/artyom/tags/pull-sun4v-20170118: (30 commits)
target-sparc: fix up niagara machine
target-sparc: move common cpu initialisation routines to sparc64.c
target-sparc: implement sun4v RTC
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
target-sparc: store the UA2005 entries in sun4u format
target-sparc: implement UA2005 ASI_MMU (0x21)
target-sparc: add more registers to dump_mmu
target-sparc: implement auto-demapping for UA2005 CPUs
target-sparc: allow 256M sized pages
target-sparc: simplify ultrasparc_tsb_pointer
target-sparc: implement UA2005 TSB Pointers
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
target-sparc: replace the last tlb entry when no free entries left
target-sparc: ignore writes to UA2005 CPU mondo queue register
target-sparc: allow priveleged ASIs in hyperprivileged mode
target-sparc: use direct address translation in hyperprivileged mode
target-sparc: fix immediate UA2005 traps
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
target-sparc: implement UA2005 GL register
target-sparc: implement UA2005 hypervisor traps
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
|
Revision tags: ppc-for-2.9-20170112, master-20170112, v2.7.1, v2.8.0, v2.8.0-rc4, v2.8.0-rc3, ppc-for-2.8-20161201, v2.8.0-rc2, ppc-for-2.8-20161123, v2.8.0-rc1, isa-cleanup-20161118, qemu-kvm-1.5.3-127.el7, v2.8.0-rc0, ppc-for-2.8-20161115, qemu-kvm-1.5.3-126.el7_3.1, qemu-kvm-0.12.1.2-2.496.el6, ppc-for-2.8-20161028, qemu-kvm-0.12.1.2-2.495.el6, ppc-for-2.8-20161026, ppc-for-2.8-20161017, qemu-kvm-rhev-2.3.0-31.el7_2.23, ppc-for-2.7-20161013, qemu-kvm-1.5.3-105.el7_2.10, ppc-for-2.8-20161006, qemu-kvm-1.5.3-105.el7_2.9, v2.6.2, RHELSA-7.3_qemu-kvm-rhev, qemu-kvm-rhev-2.6.0-28.el7, RHEL-7.3_qemu-kvm-rhev, qemu-kvm-rhev-2.6.0-27.el7, ppc-for-2.8-20160923, qemu-kvm-0.12.1.2-2.494.el6, ppc-for-2.8-20160922, RHEL-7.3_qemu-kvm, qemu-kvm-1.5.3-126.el7, qemu-kvm-rhev-2.6.0-26.el7, vfio-fixes-20160915.0, qemu-kvm-1.5.3-125.el7, qemu-kvm-rhev-2.3.0-31.el7_2.22, qemu-kvm-rhev-2.6.0-25.el7, qemu-kvm-1.5.3-124.el7, qemu-kvm-rhev-2.6.0-24.el7, qemu-kvm-1.5.3-123.el7, qemu-kvm-0.12.1.2-2.415.el6_5.16, ppc-for-2.8-20160907, qemu-kvm-rhev-2.6.0-23.el7, ppc-for-2.8-20160906, v2.7.0, RHEL-7.3-qemu-guest-agent, qemu-guest-agent-2.5.0-3.el7, v2.7.0-rc5, qemu-kvm-1.5.3-122.el7, qemu-kvm-rhev-2.6.0-22.el7, v2.7.0-rc4, v2.6.1, v2.7.0-rc3, qemu-kvm-rhev-2.6.0-21.el7, qemu-kvm-1.5.3-105.el7_2.8, ppc-for-2.7-20160815, qemu-kvm-rhev-2.6.0-20.el7, ppc-for-2.7-20160810, v2.7.0-rc2, ppc-for-2.7-20160808, qemu-kvm-rhev-2.6.0-19.el7, ppc-for-2.7-20160803, qemu-kvm-rhev-2.6.0-18.el7, qemu-kvm-1.5.3-105.el7_2.7, qemu-kvm-rhev-2.3.0-31.el7_2.21, qemu-kvm-1.5.3-121.el7, v2.7.0-rc1, qemu-kvm-rhev-2.6.0-17.el7, qemu-kvm-1.5.3-120.el7, ppc-for-2.7-20160729, qemu-kvm-0.12.1.2-2.493.el6, qemu-kvm-1.5.3-105.el7_2.6, qemu-kvm-0.12.1.2-2.491.el6_8.3, qemu-kvm-rhev-2.3.0-31.el7_2.20, qemu-kvm-1.5.3-119.el7, qemu-kvm-rhev-2.6.0-16.el7, ppc-for-2.7-20160726, v2.7.0-rc0, qemu-kvm-rhev-2.6.0-15.el7, qemu-kvm-rhev-2.3.0-31.el7_2.19, qemu-kvm-rhev-2.6.0-14.el7, qemu-kvm-1.5.3-118.el7, vfio-update-20160718.0, ppc-for-2.7-20160718, qemu-kvm-1.5.3-117.el7, qemu-kvm-rhev-2.6.0-13.el7, qemu-kvm-rhev-2.6.0-12.el7, qemu-kvm-rhev-2.3.0-31.el7_2.18, ppc-for-2.7-20160705, qemu-kvm-rhev-2.6.0-11.el7, qemu-kvm-1.5.3-105.el7_2.5, ppc-for-2.7-20160701, vfio-update-20160630.0, qemu-kvm-0.12.1.2-2.492.el6, qemu-kvm-rhev-2.6.0-10.el7, qemu-kvm-rhev-2.3.0-31.el7_2.17, qemu-kvm-1.5.3-116.el7, ppc-for-2.7-20160627, qemu-kvm-rhev-2.6.0-9.el7, ppc-for-2.7-20160623, qemu-kvm-0.12.1.2-2.491.el6_8.2, qemu-kvm-rhev-2.6.0-8.el7, qemu-kvm-1.5.3-115.el7, ppc-for-2.7-20160617, qemu-kvm-rhev-2.3.0-31.el7_2.16, qemu-kvm-rhev-2.6.0-7.el7, qemu-kvm-rhev-2.6.0-6.el7, qemu-kvm-1.5.3-114.el7, qemu-guest-agent-2.5.0-2.el7, ppc-for-2.7-20160614 |
|
| #
cbc3a6a4 |
| 07-Jun-2016 |
Artyom Tarasenko <atar4qemu@gmail.com> |
target-sparc: implement UA2005 GL register
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
|
| #
0f2d17c1 |
| 12-Jan-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170110' into staging
TCG opcodes for extract, clz, ctz, ctpop
# gpg: Signature made Wed 11 Jan 2017 02:12:41 GMT
# gpg: usin
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170110' into staging
TCG opcodes for extract, clz, ctz, ctpop
# gpg: Signature made Wed 11 Jan 2017 02:12:41 GMT
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-tcg-20170110: (65 commits)
tcg/i386: Handle ctpop opcode
tcg/ppc: Handle ctpop opcode
tcg: Use ctpop to generate ctz if needed
tests: New test-bitcnt
qemu/host-utils.h: Reduce the operation count in the fallback ctpop
target-i386: Use ctpop helper
target-tilegx: Use ctpop helper
target-sparc: Use ctpop helper
target-s390x: Avoid a loop for popcnt
target-ppc: Use ctpop helper
target-alpha: Use ctpop helper
tcg: Add opcode for ctpop
target-xtensa: Use clrsb helper
target-tricore: Use clrsb helper
target-arm: Use clrsb helper
tcg: Add helpers for clrsb
tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR
tcg/i386: Handle ctz and clz opcodes
tcg/i386: Allow bmi2 shiftx to have non-matching operands
tcg/i386: Hoist common arguments in tcg_out_op
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
08da3180 |
| 21-Nov-2016 |
Richard Henderson <rth@twiddle.net> |
target-sparc: Use ctpop helper
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
|
| #
d1e8e8ec |
| 21-Dec-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/huth/tags/target-dirs-20161220' into staging
Move target-xxx folders to target/ directory
# gpg: Signature made Tue 20 Dec 2016 21:00:39 GMT
# gpg:
Merge remote-tracking branch 'remotes/huth/tags/target-dirs-20161220' into staging
Move target-xxx folders to target/ directory
# gpg: Signature made Tue 20 Dec 2016 21:00:39 GMT
# gpg: using RSA key 0x2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>"
# gpg: aka "Thomas Huth <thuth@redhat.com>"
# gpg: aka "Thomas Huth <huth@tuxfamily.org>"
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/huth/tags/target-dirs-20161220:
Move target-* CPU file into a target/ folder
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|