Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Support building Arm targets with CONFIG_TCG=no (ie KVM only)
* hw/net: n

Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Support building Arm targets with CONFIG_TCG=no (ie KVM only)
* hw/net: npcm7xx_emc: set MAC in register space
* hw/arm/bcm2835_property: Implement "get command line" message
* Deprecate the '-singlestep' command line option in favour of
'-one-insn-per-tb' and '-accel one-insn-per-tb=on'
* Deprecate 'singlestep' member of QMP StatusInfo struct
* docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation
* hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()
* raspi, aspeed: Write bootloader code correctly on big-endian hosts
* hw/intc/allwinner-a10-pic: Fix bug on big-endian hosts
* Fix bug in A32 ERET on big-endian hosts that caused guest crash
* hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields
* hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields

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# gpg: Signature made Tue 02 May 2023 03:48:10 PM BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm: (34 commits)
hw/net/allwinner-sun8i-emac: Correctly byteswap descriptor fields
hw/sd/allwinner-sdhost: Correctly byteswap descriptor fields
target/arm: Add compile time asserts to load/store_cpu_field macros
target/arm: Define and use new load_cpu_field_low32()
hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()
hw/arm/raspi: Use arm_write_bootloader() to write boot code
hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader
hw/arm/boot: Make write_bootloader() public as arm_write_bootloader()
hw/net/msf2-emac: Don't modify descriptor in-place in emac_store_desc()
docs/about/deprecated.rst: Add "since 7.1" tag to dtb-kaslr-seed deprecation
qmp: Deprecate 'singlestep' member of StatusInfo
qapi/run-state.json: Fix missing newline at end of file
hmp: Add 'one-insn-per-tb' command equivalent to 'singlestep'
accel/tcg: Report one-insn-per-tb in 'info jit', not 'info status'
Document that -singlestep command line option is deprecated
bsd-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'
linux-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'
accel/tcg: Use one_insn_per_tb global instead of old singlestep global
softmmu: Don't use 'singlestep' global in QMP and HMP commands
make one-insn-per-tb an accel option
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/arm: Define and use new load_cpu_field_low32()

In several places in the 32-bit Arm translate.c, we try to use
load_cpu_field() to load from a CPUARMState field into a TCGv_i32
where the field

target/arm: Define and use new load_cpu_field_low32()

In several places in the 32-bit Arm translate.c, we try to use
load_cpu_field() to load from a CPUARMState field into a TCGv_i32
where the field is actually 64-bit. This works on little-endian
hosts, but gives the wrong half of the register on big-endian.

Add a new load_cpu_field_low32() which loads the low 32 bits
of a 64-bit field into a TCGv_i32. The new macro includes a
compile-time check against accidentally using it on a field
of the wrong size. Use it to fix the two places in the code
where we were using load_cpu_field() on a 64-bit field.

This fixes a bug where on big-endian hosts the guest would
crash after executing an ERET instruction, and a more corner
case one where some UNDEFs for attempted accesses to MSR
banked registers from Secure EL1 might go to the wrong EL.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org

show more ...

Merge tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

* target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()
* hw/arm: do not free mach

Merge tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

* target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()
* hw/arm: do not free machine->fdt in arm_load_dtb()
* target/arm: Fix generated code for cpreg reads when HSTR is active
* hw/ssi: Fix Linux driver init issue with xilinx_spi

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# gpg: Signature made Mon 03 Apr 2023 17:00:44 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm:
hw/ssi: Fix Linux driver init issue with xilinx_spi
target/arm: Fix generated code for cpreg reads when HSTR is active
hw/arm: do not free machine->fdt in arm_load_dtb()
target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/arm: Fix generated code for cpreg reads when HSTR is active

In commit 049edada we added some code to handle HSTR_EL2 traps, which
we did as an inline "conditionally branch over a
gen_exceptio

target/arm: Fix generated code for cpreg reads when HSTR is active

In commit 049edada we added some code to handle HSTR_EL2 traps, which
we did as an inline "conditionally branch over a
gen_exception_insn()". Unfortunately this fails to take account of
the fact that gen_exception_insn() will set s->base.is_jmp to
DISAS_NORETURN. That means that at the end of the TB we won't
generate the necessary code to handle the "branched over the trap and
continued normal execution" codepath. The result is that the TCG
main loop thinks that we stopped execution of the TB due to a
situation that only happens when icount is enabled, and hits an
assertion. Explicitly set is_jmp back to DISAS_NEXT so we generate
the correct code for when execution continues past this insn.

Note that this only happens for cpreg reads; writes will call
gen_lookup_tb() which generates a valid end-of-TB.

Fixes: 049edada ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1551
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230330101900.2320380-1-peter.maydell@linaro.org

show more ...

Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/

Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const

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# gpg: Signature made Mon 13 Mar 2023 18:55:57 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits)
tcg: Drop tcg_const_*
tcg: Drop tcg_const_*_vec
target/tricore: Use min/max for saturate
target/ppc: Avoid tcg_const_* in translate.c
target/ppc: Fix gen_tlbsx_booke206
target/ppc: Rewrite trans_ADDG6S
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
target/ppc: Avoid tcg_const_* in xxeval
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
target/ppc: Avoid tcg_const_i64 in do_vcntmb
target/m68k: Use tcg_constant_i32 in gen_ea_mode
target/arm: Avoid tcg_const_ptr in handle_rev
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
target/arm: Avoid tcg_const_* in translate-mve.c
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
target/arm: Improve trans_BFCI
target/arm: Create gen_set_rmode, gen_restore_rmode
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/arm: Improve trans_BFCI

Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.

Reviewed-by: Philippe

target/arm: Improve trans_BFCI

Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging

tcg: Merge two sequential labels
accel/tcg: Retain prot flags from tlb_fill
accel/tcg: Honor TLB_DISCARD_WRITE in atomic

Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging

tcg: Merge two sequential labels
accel/tcg: Retain prot flags from tlb_fill
accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup
accel/tcg: Honor TLB_WATCHPOINTS in atomic_mmu_lookup
target/sparc: Use tlb_set_page_full
include/qemu/cpuid: Introduce xgetbv_low
tcg/i386: Mark Win64 call-saved vector regs as reserved
tcg: Decode the operand to INDEX_op_mb in dumps

Portion of the target/ patchset which eliminates use of tcg_temp_free*
Portion of the target/ patchset which eliminates use of tcg_const*

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# gpg: Signature made Mon 06 Mar 2023 00:38:00 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu: (84 commits)
target/xtensa: Avoid tcg_const_i32
target/xtensa: Split constant in bit shift
target/xtensa: Use tcg_gen_subfi_i32 in translate_sll
target/xtensa: Avoid tcg_const_i32 in translate_l32r
target/xtensa: Tidy translate_clamps
target/xtensa: Tidy translate_bb
target/sparc: Avoid tcg_const_{tl,i32}
target/s390x: Split out gen_ri2
target/riscv: Avoid tcg_const_*
target/microblaze: Avoid tcg_const_* throughout
target/i386: Simplify POPF
target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op
target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred
target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign
target/hexagon/idef-parser: Use gen_tmp for LPCFG
target/hexagon: Use tcg_constant_* for gen_constant_from_imm
docs/devel/tcg-ops: Drop recommendation to free temps
tracing: remove transform.py
include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start
target/tricore: Drop tcg_temp_free
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/arm: Drop tcg_temp_free from translator.c

Translators are no longer required to free tcg temporaries.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <

target/arm: Drop tcg_temp_free from translator.c

Translators are no longer required to free tcg temporaries.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/arm: Remove value_global from DisasCompare

This field was only used to avoid freeing globals.
Since we no longer free any temps, this is dead.

Reviewed-by: Peter Maydell <peter.maydell@linar

target/arm: Remove value_global from DisasCompare

This field was only used to avoid freeing globals.
Since we no longer free any temps, this is dead.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/arm: Remove arm_free_cc, a64_free_cc

Translators are no longer required to free tcg temporaries.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richa

target/arm: Remove arm_free_cc, a64_free_cc

Translators are no longer required to free tcg temporaries.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

accel/tcg: Remove translator_loop_temp_check

Finish removing tcg temp free accounting interfaces.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.hen

accel/tcg: Remove translator_loop_temp_check

Finish removing tcg temp free accounting interfaces.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging

helper-head: Add fpu/softfloat-types.h
softmmu: Use memmove in flatview_write_continue
tcg: Add sign param to probe_acce

Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging

helper-head: Add fpu/softfloat-types.h
softmmu: Use memmove in flatview_write_continue
tcg: Add sign param to probe_access_flags, probe_access_full
tcg: Convert TARGET_TB_PCREL to CF_PCREL
tcg: Simplify temporary lifetimes for translators

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# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu: (62 commits)
tcg: Update docs/devel/tcg-ops.rst for temporary changes
tcg: Remove tcg_temp_local_new_*, tcg_const_local_*
exec/gen-icount: Don't use tcg_temp_local_new_i32
target/xtensa: Don't use tcg_temp_local_new_*
target/ppc: Don't use tcg_temp_local_new
target/mips: Don't use tcg_temp_local_new
target/i386: Don't use tcg_temp_local_new
target/hppa: Don't use tcg_temp_local_new
target/hexagon/idef-parser: Drop gen_tmp_local
target/hexagon: Don't use tcg_temp_local_new_*
target/cris: Don't use tcg_temp_local_new
target/arm: Don't use tcg_temp_local_new_*
target/arm: Drop copies in gen_sve_{ldr,str}
tcg: Change default temp lifetime to TEMP_TB
tcg: Don't re-use TEMP_TB temporaries
accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers
accel/tcg/plugin: Use tcg_temp_ebb_*
tcg: Use tcg_constant_ptr in do_dup
tcg: Use tcg_temp_ebb_new_* in tcg/
tcg: Add tcg_temp_ebb_new_{i32,i64,ptr}
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/arm: Don't use tcg_temp_local_new_*

Since tcg_temp_new_* is now identical, use those.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.hender

target/arm: Don't use tcg_temp_local_new_*

Since tcg_temp_new_* is now identical, use those.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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accel/tcg: Pass max_insn to gen_intermediate_code by pointer

In preparation for returning the number of insns generated
via the same pointer. Adjust only the prototypes so far.

Reviewed-by: Philip

accel/tcg: Pass max_insn to gen_intermediate_code by pointer

In preparation for returning the number of insns generated
via the same pointer. Adjust only the prototypes so far.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL`

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230227135202.9710-7-anjo@rev

target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL`

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230227135202.9710-7-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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Merge tag 'pull-target-arm-20230227' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Various code cleanups
* More refactoring working towards allowing a build

Merge tag 'pull-target-arm-20230227' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* Various code cleanups
* More refactoring working towards allowing a build
without CONFIG_TCG

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# gpg: Signature made Mon 27 Feb 2023 13:59:09 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230227' of https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits)
hw: Replace qemu_or_irq typedef by OrIRQState
hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
hw/arm/musicpal: Remove unused dummy MemoryRegion
hw/intc/armv7m_nvic: Use QOM cast CPU() macro
hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
hw/char/pl011: Open-code pl011_luminary_create()
hw/char/pl011: Un-inline pl011_create()
hw/gpio/max7310: Simplify max7310_realize()
tests/avocado: add machine:none tag to version.py
cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
target/arm: Don't access TCG code when debugging with KVM
target/arm: Move regime_using_lpae_format into internal.h
target/arm: Move hflags code into the tcg directory
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
target/arm: Move psci.c into the tcg directory
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/arm: move translate modules to tcg/

Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
code that is selected by CONFIG_TCG.

Signed-off-by: Claudio Fontana <cfontana@suse.

target/arm: move translate modules to tcg/

Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
code that is selected by CONFIG_TCG.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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