Merge branch 'remotes/lorenzo/pci/cadence'

- Convert cadence to use standard "dma-ranges" DT property instead of its
own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I)

- Fix pm_runtime_put_sy

Merge branch 'remotes/lorenzo/pci/cadence'

- Convert cadence to use standard "dma-ranges" DT property instead of its
own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I)

- Fix pm_runtime_put_sync() issues in cadence error paths (Kishon Vijay
Abraham I)

- Add PTR_ALIGN_DOWN macro (Kishon Vijay Abraham I)

- Convert cadence r/w accessors to only 32-bit accesses (Kishon Vijay
Abraham I)

- Add cadence support to start Link and check Link status (Kishon Vijay
Abraham I)

- Allow custom PCI ops for cadence-based drivers (Kishon Vijay Abraham I)

- Remove "mem" from cadence reg binding since it's not memory and it
overlaps the PCIe config and memory region (Kishon Vijay Abraham I)

- Add cadence ->cpu_addr_fixup() for platforms that require absolute
addresses in the ATU, not just offsets (Kishon Vijay Abraham I)

- Update cadence Vendor IDs using local management registers, not
architected config space (Kishon Vijay Abraham I)

- Add cadence endpoint driver MSI-X support (Kishon Vijay Abraham I)

- Add bindings and driver for TI J721E SoC, supporting both host and
endpoint mode (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/cadence:
MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe
misc: pci_endpoint_test: Add J721E in pci_device_id table
PCI: j721e: Add TI J721E PCIe driver
dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
PCI: cadence: Add MSI-X support to Endpoint driver
PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register
PCI: cadence: Add new *ops* for CPU addr fixup
dt-bindings: PCI: cadence: Remove "mem" from reg binding
PCI: cadence: Allow pci_host_bridge to have custom pci_ops
PCI: cadence: Add support to start link and verify link status
PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
linux/kernel.h: Add PTR_ALIGN_DOWN macro
PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property

show more ...

PCI: cadence: Add new *ops* for CPU addr fixup

Cadence driver uses "mem" memory resource to obtain the offset of
configuration space address region, memory space address region and
message space add

PCI: cadence: Add new *ops* for CPU addr fixup

Cadence driver uses "mem" memory resource to obtain the offset of
configuration space address region, memory space address region and
message space address region. The obtained offset is used to program
the Address Translation Unit (ATU). However certain platforms like TI's
J721E SoC require the absolute address to be programmed in the ATU and
not just the offset. Add new *ops* for CPU addr fixup for the platform
drivers to provide the correct address to be programmed in the ATU.

Link: https://lore.kernel.org/r/20200722110317.4744-9-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

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PCI: cadence: Remove private bus number and range storage

There's no need to store the bus number or range resource as the driver
only needs the bus number which is already in the pci_host_bridge.

PCI: cadence: Remove private bus number and range storage

There's no need to store the bus number or range resource as the driver
only needs the bus number which is already in the pci_host_bridge.

For endpoint mode, the bus number is always 0.

Link: https://lore.kernel.org/r/20200722022514.1283916-14-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tom Joseph <tjoseph@cadence.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>

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Merge drm-intel-next-queued into gvt-next

Backmerge to pull in
https://patchwork.freedesktop.org/patch/353621/?series=73544&rev=1

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

Merge tag 'v5.5-rc4' into locking/kcsan, to resolve conflicts

Conflicts:
init/main.c
lib/Kconfig.debug

Signed-off-by: Ingo Molnar <mingo@kernel.org>

Merge branch 'next' into for-linus

Prepare input updates for 5.6 merge window.

Merge tag 'v5.5-rc5' into next

Sync up with mainline to get SPI "delay" API changes.

Merge drm/drm-next into drm-misc-next

Requested, and we need v5.5-rc1 backported as our current branch is still based on v5.4.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Merge tag 'perf-urgent-for-mingo-5.5-20191216' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent

Pull perf/urgent fixes:

perf top:

Arnaldo Carvalho de Melo:

- Do not

Merge tag 'perf-urgent-for-mingo-5.5-20191216' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent

Pull perf/urgent fixes:

perf top:

Arnaldo Carvalho de Melo:

- Do not bail out when perf_env__read_cpuid() returns ENOSYS, which
has been reported happening on aarch64.

perf metricgroup:

Kajol Jain:

- Fix printing event names of metric group with multiple events

vendor events:

x86:

Ravi Bangoria:

- Fix Kernel_Utilization metric.

s390:

Ed Maste:

- Fix counter long description for DTLB1_GPAGE_WRITES and L1D_RO_EXCL_WRITES.

perf header:

Michael Petlan:

- Fix false warning when there are no duplicate cache entries

libtraceevent:

Sudip Mukherjee:

- Allow custom libdir path

API headers:

Arnaldo Carvalho de Melo:

- Sync linux/kvm.h with the kernel sources.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>

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Merge remote-tracking branch 'torvalds/master' into perf/urgent

To pick up BPF fixes to allow a clean 'make -C tools/perf build-test':

7c3977d1e804 libbpf: Fix sym->st_value print on 32-bit arche

Merge remote-tracking branch 'torvalds/master' into perf/urgent

To pick up BPF fixes to allow a clean 'make -C tools/perf build-test':

7c3977d1e804 libbpf: Fix sym->st_value print on 32-bit arches
1fd450f99272 libbpf: Fix up generation of bpf_helper_defs.h

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

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Merge drm/drm-next into drm-intel-next-queued

Sync up with v5.5-rc1 to get the updated lock_release() API among other
things. Fix the conflict reported by Stephen Rothwell [1].

[1] http://lore.kern

Merge drm/drm-next into drm-intel-next-queued

Sync up with v5.5-rc1 to get the updated lock_release() API among other
things. Fix the conflict reported by Stephen Rothwell [1].

[1] http://lore.kernel.org/r/20191210093957.5120f717@canb.auug.org.au

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

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Merge tag 'v5.5-rc1' into core/kprobes, to resolve conflicts

Signed-off-by: Ingo Molnar <mingo@kernel.org>

Merge branch 'linus' into sched/urgent, to pick up the latest before merging new patches

Signed-off-by: Ingo Molnar <mingo@kernel.org>

Merge mainline/master into arm/fixes

This brings in the mainline tree right after armsoc contents was merged
this release cycle, so that we can re-run savedefconfig, etc.

Signed-off-by: Olof Johans

Merge mainline/master into arm/fixes

This brings in the mainline tree right after armsoc contents was merged
this release cycle, so that we can re-run savedefconfig, etc.

Signed-off-by: Olof Johansson <olof@lixom.net>

show more ...

Merge tag 'pci-v5.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
"Enumeration:

- Warn if a host bridge has no NUMA info (Yunsheng L

Merge tag 'pci-v5.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
"Enumeration:

- Warn if a host bridge has no NUMA info (Yunsheng Lin)

- Add PCI_STD_NUM_BARS for the number of standard BARs (Denis
Efremov)

Resource management:

- Fix boot-time Embedded Controller GPE storm caused by incorrect
resource assignment after ACPI Bus Check Notification (Mika
Westerberg)

- Protect pci_reassign_bridge_resources() against concurrent
addition/removal (Benjamin Herrenschmidt)

- Fix bridge dma_ranges resource list cleanup (Rob Herring)

- Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters to control
the MMIO and prefetchable MMIO window sizes of hotplug bridges
independently (Nicholas Johnson)

- Fix MMIO/MMIO_PREF window assignment that assigned more space than
desired (Nicholas Johnson)

- Only enforce bus numbers from bridge EA if the bridge has EA
devices downstream (Subbaraya Sundeep)

- Consolidate DT "dma-ranges" parsing and convert all host drivers to
use shared parsing (Rob Herring)

Error reporting:

- Restore AER capability after resume (Mayurkumar Patel)

- Add PoisonTLPBlocked AER counter (Rajat Jain)

- Use for_each_set_bit() to simplify AER code (Andy Shevchenko)

- Fix AER kernel-doc (Andy Shevchenko)

- Add "pcie_ports=dpc-native" parameter to allow native use of DPC
even if platform didn't grant control over AER (Olof Johansson)

Hotplug:

- Avoid returning prematurely from sysfs requests to enable or
disable a PCIe hotplug slot (Lukas Wunner)

- Don't disable interrupts twice when suspending hotplug ports (Mika
Westerberg)

- Fix deadlocks when PCIe ports are hot-removed while suspended (Mika
Westerberg)

Power management:

- Remove unnecessary ASPM locking (Bjorn Helgaas)

- Add support for disabling L1 PM Substates (Heiner Kallweit)

- Allow re-enabling Clock PM after it has been disabled (Heiner
Kallweit)

- Add sysfs attributes for controlling ASPM link states (Heiner
Kallweit)

- Remove CONFIG_PCIEASPM_DEBUG, including "link_state" and "clk_ctl"
sysfs files (Heiner Kallweit)

- Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on
USB 2.0 or 1.1 connect events (Kai-Heng Feng)

- Move power state check out of pci_msi_supported() (Bjorn Helgaas)

- Fix incorrect MSI-X masking on resume and revert related nvme quirk
for Kingston NVME SSD running FW E8FK11.T (Jian-Hong Pan)

- Always return devices to D0 when thawing to fix hibernation with
drivers like mlx4 that used legacy power management (previously we
only did it for drivers with new power management ops) (Dexuan Cui)

- Clear PCIe PME Status even for legacy power management (Bjorn
Helgaas)

- Fix PCI PM documentation errors (Bjorn Helgaas)

- Use dev_printk() for more power management messages (Bjorn Helgaas)

- Apply D2 delay as milliseconds, not microseconds (Bjorn Helgaas)

- Convert xen-platform from legacy to generic power management (Bjorn
Helgaas)

- Removed unused .resume_early() and .suspend_late() legacy power
management hooks (Bjorn Helgaas)

- Rearrange power management code for clarity (Rafael J. Wysocki)

- Decode power states more clearly ("4" or "D4" really refers to
"D3cold") (Bjorn Helgaas)

- Notice when reading PM Control register returns an error (~0)
instead of interpreting it as being in D3hot (Bjorn Helgaas)

- Add missing link delays required by the PCIe spec (Mika Westerberg)

Virtualization:

- Move pci_prg_resp_pasid_required() to CONFIG_PCI_PRI (Bjorn
Helgaas)

- Allow VFs to use PRI (the PF PRI is shared by the VFs, but the code
previously didn't recognize that) (Kuppuswamy Sathyanarayanan)

- Allow VFs to use PASID (the PF PASID capability is shared by the
VFs, but the code previously didn't recognize that) (Kuppuswamy
Sathyanarayanan)

- Disconnect PF and VF ATS enablement, since ATS in PFs and
associated VFs can be enabled independently (Kuppuswamy
Sathyanarayanan)

- Cache PRI and PASID capability offsets (Kuppuswamy Sathyanarayanan)

- Cache the PRI PRG Response PASID Required bit (Bjorn Helgaas)

- Consolidate ATS declarations in linux/pci-ats.h (Krzysztof
Wilczynski)

- Remove unused PRI and PASID stubs (Bjorn Helgaas)

- Removed unnecessary EXPORT_SYMBOL_GPL() from ATS, PRI, and PASID
interfaces that are only used by built-in IOMMU drivers (Bjorn
Helgaas)

- Hide PRI and PASID state restoration functions used only inside the
PCI core (Bjorn Helgaas)

- Add a DMA alias quirk for the Intel VCA NTB (Slawomir Pawlowski)

- Serialize sysfs sriov_numvfs reads vs writes (Pierre Crégut)

- Update Cavium ACS quirk for ThunderX2 and ThunderX3 (George
Cherian)

- Fix the UPDCR register address in the Intel ACS quirk (Steffen
Liebergeld)

- Unify ACS quirk implementations (Bjorn Helgaas)

Amlogic Meson host bridge driver:

- Fix meson PERST# GPIO polarity problem (Remi Pommarel)

- Add DT bindings for Amlogic Meson G12A (Neil Armstrong)

- Fix meson clock names to match DT bindings (Neil Armstrong)

- Add meson support for Amlogic G12A SoC with separate shared PHY
(Neil Armstrong)

- Add meson extended PCIe PHY functions for Amlogic G12A USB3+PCIe
combo PHY (Neil Armstrong)

- Add arm64 DT for Amlogic G12A PCIe controller node (Neil Armstrong)

- Add commented-out description of VIM3 USB3/PCIe mux in arm64 DT
(Neil Armstrong)

Broadcom iProc host bridge driver:

- Invalidate iProc PAXB address mapping before programming it
(Abhishek Shah)

- Fix iproc-msi and mvebu __iomem annotations (Ben Dooks)

Cadence host bridge driver:

- Refactor Cadence PCIe host controller to use as a library for both
host and endpoint (Tom Joseph)

Freescale Layerscape host bridge driver:

- Add layerscape LS1028a support (Xiaowei Bao)

Intel VMD host bridge driver:

- Add VMD bus 224-255 restriction decode (Jon Derrick)

- Add VMD 8086:9A0B device ID (Jon Derrick)

- Remove Keith from VMD maintainer list (Keith Busch)

Marvell ARMADA 3700 / Aardvark host bridge driver:

- Use LTSSM state to build link training flag since Aardvark doesn't
implement the Link Training bit (Remi Pommarel)

- Delay before training Aardvark link in case PERST# was asserted
before the driver probe (Remi Pommarel)

- Fix Aardvark issues with Root Control reads and writes (Remi
Pommarel)

- Don't rely on jiffies in Aardvark config access path since
interrupts may be disabled (Remi Pommarel)

- Fix Aardvark big-endian support (Grzegorz Jaszczyk)

Marvell ARMADA 370 / XP host bridge driver:

- Make mvebu_pci_bridge_emul_ops static (Ben Dooks)

Microsoft Hyper-V host bridge driver:

- Add hibernation support for Hyper-V virtual PCI devices (Dexuan
Cui)

- Track Hyper-V pci_protocol_version per-hbus, not globally (Dexuan
Cui)

- Avoid kmemleak false positive on hv hbus buffer (Dexuan Cui)

Mobiveil host bridge driver:

- Change mobiveil csr_read()/write() function names that conflict
with riscv arch functions (Kefeng Wang)

NVIDIA Tegra host bridge driver:

- Fix Tegra CLKREQ dependency programming (Vidya Sagar)

Renesas R-Car host bridge driver:

- Remove unnecessary header include from rcar (Andrew Murray)

- Tighten register index checking for rcar inbound range programming
(Marek Vasut)

- Fix rcar inbound range alignment calculation to improve packing of
multiple entries (Marek Vasut)

- Update rcar MACCTLR setting to match documentation (Yoshihiro
Shimoda)

- Clear bit 0 of MACCTLR before PCIETCTLR.CFINIT per manual
(Yoshihiro Shimoda)

- Add Marek Vasut and Yoshihiro Shimoda as R-Car maintainers (Simon
Horman)

Rockchip host bridge driver:

- Make rockchip 0V9 and 1V8 power regulators non-optional (Robin
Murphy)

Socionext UniPhier host bridge driver:

- Set uniphier to host (RC) mode always (Kunihiko Hayashi)

Endpoint drivers:

- Fix endpoint driver sign extension problem when shifting page
number to phys_addr_t (Alan Mikhak)

Misc:

- Add NumaChip SPDX header (Krzysztof Wilczynski)

- Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski)

- Remove unused includes (Krzysztof Wilczynski)

- Removed unused sysfs attribute groups (Ben Dooks)

- Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas)

- Add PCIe Link Control 2 register field definitions to replace magic
numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas)

- Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and
Radeon CIK/SI PCIe Gen3 link training (Bjorn Helgaas)

- Use pcie_capability_read_word() instead of pci_read_config_word()
in AMDGPU and Radeon CIK/SI (Frederick Lawler)

- Remove unused pci_irq_get_node() Greg Kroah-Hartman)

- Make asm/msi.h mandatory and simplify PCI_MSI_IRQ_DOMAIN Kconfig
(Palmer Dabbelt, Michal Simek)

- Read all 64 bits of Switchtec part_event_bitmap (Logan Gunthorpe)

- Fix erroneous intel-iommu dependency on CONFIG_AMD_IOMMU (Bjorn
Helgaas)

- Fix bridge emulation big-endian support (Grzegorz Jaszczyk)

- Fix dwc find_next_bit() usage (Niklas Cassel)

- Fix pcitest.c fd leak (Hewenliang)

- Fix typos and comments (Bjorn Helgaas)

- Fix Kconfig whitespace errors (Krzysztof Kozlowski)"

* tag 'pci-v5.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (160 commits)
PCI: Remove PCI_MSI_IRQ_DOMAIN architecture whitelist
asm-generic: Make msi.h a mandatory include/asm header
Revert "nvme: Add quirk for Kingston NVME SSD running FW E8FK11.T"
PCI/MSI: Fix incorrect MSI-X masking on resume
PCI/MSI: Move power state check out of pci_msi_supported()
PCI/MSI: Remove unused pci_irq_get_node()
PCI: hv: Avoid a kmemleak false positive caused by the hbus buffer
PCI: hv: Change pci_protocol_version to per-hbus
PCI: hv: Add hibernation support
PCI: hv: Reorganize the code in preparation of hibernation
MAINTAINERS: Remove Keith from VMD maintainer
PCI/ASPM: Remove PCIEASPM_DEBUG Kconfig option and related code
PCI/ASPM: Add sysfs attributes for controlling ASPM link states
PCI: Fix indentation
drm/radeon: Prefer pcie_capability_read_word()
drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/radeon: Correct Transmit Margin masks
drm/amdgpu: Prefer pcie_capability_read_word()
PCI: uniphier: Set mode register to host mode
drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions
...

show more ...

Merge branch 'remotes/lorenzo/pci/cadence'

- Refactor Cadence PCIe host controller to use as a library for both host
and endpoint (Tom Joseph)

* remotes/lorenzo/pci/cadence:
PCI: cadence: M

Merge branch 'remotes/lorenzo/pci/cadence'

- Refactor Cadence PCIe host controller to use as a library for both host
and endpoint (Tom Joseph)

* remotes/lorenzo/pci/cadence:
PCI: cadence: Move all files to per-device cadence directory
PCI: cadence: Refactor driver to use as a core library

show more ...

PCI: cadence: Move all files to per-device cadence directory

Cadence core library files may be used by various platform drivers.
Add a new directory "cadence" to group all the Cadence core library f

PCI: cadence: Move all files to per-device cadence directory

Cadence core library files may be used by various platform drivers.
Add a new directory "cadence" to group all the Cadence core library files
and the platforms using Cadence core library.

Signed-off-by: Tom Joseph <tjoseph@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>

show more ...