History log of /openbmc/linux/arch/riscv/include/asm/atomic.h (Results 176 – 190 of 190)
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# 7b47c66c 04-Dec-2017 Gustavo Padovan <gustavo.padovan@collabora.com>

Merge arlied/drm-next into drm-misc-next

We need to pull 66660d4cf21b (drm: add connector info/property for
non-desktop displays [v2]) into drm-misc-next to continue the development
of the display r

Merge arlied/drm-next into drm-misc-next

We need to pull 66660d4cf21b (drm: add connector info/property for
non-desktop displays [v2]) into drm-misc-next to continue the development
of the display rotation series.

Effectively this also pulls 4.15-r2 into drm-misc-next.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>

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# d218439f 04-Dec-2017 Mark Brown <broonie@kernel.org>

Merge branch 'fix/amd' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-amd


# e1ba1c99 01-Dec-2017 Linus Torvalds <torvalds@linux-foundation.org>

Merge tag 'riscv-for-linus-4.15-rc2_cleanups' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux

Pull RISC-V cleanups and ABI fixes from Palmer Dabbelt:
"This contains a handful of small

Merge tag 'riscv-for-linus-4.15-rc2_cleanups' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux

Pull RISC-V cleanups and ABI fixes from Palmer Dabbelt:
"This contains a handful of small cleanups that are a result of
feedback that didn't make it into our original patch set, either
because the feedback hadn't been given yet, I missed the original
emails, or we weren't ready to submit the changes yet.

I've been maintaining the various cleanup patch sets I have as their
own branches, which I then merged together and signed. Each merge
commit has a short summary of the changes, and each branch is based on
your latest tag (4.15-rc1, in this case). If this isn't the right way
to do this then feel free to suggest something else, but it seems sane
to me.

Here's a short summary of the changes, roughly in order of how
interesting they are.

- libgcc.h has been moved from include/lib, where it's the only
member, to include/linux. This is meant to avoid tab completion
conflicts.

- VDSO entries for clock_get/gettimeofday/getcpu have been added.
These are simple syscalls now, but we want to let glibc use them
from the start so we can make them faster later.

- A VDSO entry for instruction cache flushing has been added so
userspace can flush the instruction cache.

- The VDSO symbol versions for __vdso_cmpxchg{32,64} have been
removed, as those VDSO entries don't actually exist.

- __io_writes has been corrected to respect the given type.

- A new READ_ONCE in arch_spin_is_locked().

- __test_and_op_bit_ord() is now actually ordered.

- Various small fixes throughout the tree to enable allmodconfig to
build cleanly.

- Removal of some dead code in our atomic support headers.

- Improvements to various comments in our atomic support headers"

* tag 'riscv-for-linus-4.15-rc2_cleanups' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux: (23 commits)
RISC-V: __io_writes should respect the length argument
move libgcc.h to include/linux
RISC-V: Clean up an unused include
RISC-V: Allow userspace to flush the instruction cache
RISC-V: Flush I$ when making a dirty page executable
RISC-V: Add missing include
RISC-V: Use define for get_cycles like other architectures
RISC-V: Provide stub of setup_profiling_timer()
RISC-V: Export some expected symbols for modules
RISC-V: move empty_zero_page definition to C and export it
RISC-V: io.h: type fixes for warnings
RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
RISC-V: use generic serial.h
RISC-V: remove spin_unlock_wait()
RISC-V: `sfence.vma` orderes the instruction cache
RISC-V: Add READ_ONCE in arch_spin_is_locked()
RISC-V: __test_and_op_bit_ord should be strongly ordered
RISC-V: Remove smb_mb__{before,after}_spinlock()
RISC-V: Remove __smp_bp__{before,after}_atomic
RISC-V: Comment on why {,cmp}xchg is ordered how it is
...

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# f8182f61 01-Dec-2017 Palmer Dabbelt <palmer@sifive.com>

RISC-V Atomic Cleanups

This patch set is the result of some feedback that filtered through
after our original patch set was reviewed, some of which was the result
of me missing some email. It conta

RISC-V Atomic Cleanups

This patch set is the result of some feedback that filtered through
after our original patch set was reviewed, some of which was the result
of me missing some email. It contains:

* A new READ_ONCE in arch_spin_is_locked()
* __test_and_op_bit_ord() is now actually ordered
* Improvements to various comments
* Removal of some dead code

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# cf40a76e 28-Nov-2017 James Morris <james.l.morris@oracle.com>

Merge tag 'v4.15-rc1' into next-seccomp

Linux 4.15-rc1


# 8286d51a 28-Nov-2017 Palmer Dabbelt <palmer@sifive.com>

RISC-V: Comment on why {,cmp}xchg is ordered how it is

This is another memory model FIXME.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>


Revision tags: v4.13.16
# 4650d02a 14-Nov-2017 Palmer Dabbelt <palmer@dabbelt.com>

RISC-V: Remove unused arguments from ATOMIC_OP

Our atomics are generated from a complicated series of preprocessor
macros, each of which is slightly different from the last. When writing
the macros

RISC-V: Remove unused arguments from ATOMIC_OP

Our atomics are generated from a complicated series of preprocessor
macros, each of which is slightly different from the last. When writing
the macros I'd accidentally left some unused arguments floating around.
This patch removes the unused macro arguments.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>

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# 69830d39 28-Nov-2017 Mark Brown <broonie@kernel.org>

Merge branch 'topic/disconnect' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-rcar


# bc686442 28-Nov-2017 Tony Lindgren <tony@atomide.com>

Merge branch 'dts-fixes' into omap-for-v4.15/fixes-dt


# 2db57789 28-Nov-2017 Tony Lindgren <tony@atomide.com>

Merge branch 'soc-fixes' into omap-for-v4.15/fixes


# 088fecfb 27-Nov-2017 Mauro Carvalho Chehab <mchehab@s-opensource.com>

Merge tag 'v4.15-rc1' into patchwork

Linux 4.15-rc1

* tag 'v4.15-rc1': (12179 commits)
Linux 4.15-rc1
ARM: BUG if jumping to usermode address in kernel mode
m68k/macboing: Fix missed timer ca

Merge tag 'v4.15-rc1' into patchwork

Linux 4.15-rc1

* tag 'v4.15-rc1': (12179 commits)
Linux 4.15-rc1
ARM: BUG if jumping to usermode address in kernel mode
m68k/macboing: Fix missed timer callback assignment
afs: remove redundant assignment of dvnode to itself
afs: cell: Remove unnecessary code in afs_lookup_cell
afs: Fix signal handling in some file ops
afs: Fix some dentry handling in dir ops and missing key_puts
afs: Make afs_write_begin() avoid writing to a page that's being stored
sched/debug: Fix task state recording/printout
x86/decoder: Add new TEST instruction pattern
x86/PCI: Remove unused HyperTransport interrupt support
x86/umip: Fix insn_get_code_seg_params()'s return value
x86/boot/KASLR: Remove unused variable
genirq/matrix: Make - vs ?: Precedence explicit
irqchip/imgpdc: Use resource_size function on resource object
irqchip/qcom: Fix u32 comparison with value less than zero
ipvlan: Fix insufficient skb linear check for ipv6 icmp
ipvlan: Fix insufficient skb linear check for arp
geneve: only configure or fill UDP_ZERO_CSUM6_RX/TX info when CONFIG_IPV6
net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY
...

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# 1420edf7 27-Nov-2017 Daniel Vetter <daniel.vetter@ffwll.ch>

Merge tag 'v4.15-rc1' into drm-misc-fixes

Linux 4.15-rc1

Pull in the merge window to resync. Dave didn't get his -fixes pull
landed in time, and now there's another rockchip fix pending, so
fast-fo

Merge tag 'v4.15-rc1' into drm-misc-fixes

Linux 4.15-rc1

Pull in the merge window to resync. Dave didn't get his -fixes pull
landed in time, and now there's another rockchip fix pending, so
fast-forwarding isn't possible, hence backmerge.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

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# 866c9b94 23-Nov-2017 Thomas Gleixner <tglx@linutronix.de>

Merge tag 'for-linus-timers-conversion-final-v4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux into timers/urgent

Pull the last batch of manual timer conversions from Kees Cook:

Merge tag 'for-linus-timers-conversion-final-v4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux into timers/urgent

Pull the last batch of manual timer conversions from Kees Cook:

- final batch of "non trivial" timer conversions (multi-tree dependencies,
things Coccinelle couldn't handle, etc).

- treewide conversions via Coccinelle, in 4 steps:
- DEFINE_TIMER() functions converted to struct timer_list * argument
- init_timer() -> setup_timer()
- setup_timer() -> timer_setup()
- setup_timer() -> timer_setup() (with a single embedded structure)

- deprecated timer API removals (init_timer(), setup_*timer())

- finalization of new API (remove global casts)

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# b293fca4 15-Nov-2017 Linus Torvalds <torvalds@linux-foundation.org>

Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux

Pull RISC-V architecture support from Palmer Dabbelt:
"This contains the core RISC-V

Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux

Pull RISC-V architecture support from Palmer Dabbelt:
"This contains the core RISC-V Linux port, which has been through nine
rounds of review on various mailing lists. The port is not complete:
there's some cleanup patches moving through the review process, a
whole bunch of drivers that need some work, and a lot of feature
additions that will be needed.

The patches contained in this tag have been through nine rounds of
review on the various mailing lists. I have some outstanding cleanup
patches, but since there's been so much review on these patches I
thought it would be best to submit them as-is and then submit explicit
cleanup patches so everyone can review them. This first patch set is
big enough that it's a bit of a pain to constantly rewrite, and it's
caused a few headaches with various contributors.

The port is definately a work in progress. While what's there builds
and boots with 4.14, it's a bit hard to actually see anything happen
because there are no device drivers yet. I maintain a staging branch
that contains all the device drivers and cleanup that actually works,
but those patches won't all be ready for a while. I'd like to get what
we currently have into your tree so everyone can start working from a
single base -- of particular importance is allowing the glibc
upstreaming process to proceed so we can sort out any possibly
lingering user-visible ABI problems we might have.

Copied below is the ChangeLog that contains the history of this patch
set:

(v9) As per suggestions on our v8 patch set, I've split the core
architecture code out from our drivers and would like to submit
this patch set to be included into linux-next, with the goal
being to be merged in during the next merge window. This patch
set is based on 4.14-rc2, but if it's better to have it based on
something else then I can change it around.

This patch set contains just the core arch code for RISC-V, so
while it builds an nominally boots, you can't print or take an
interrupt so it's not that useful. If you're looking to actually
boot a system it would probably be better to use the full patch
set listed below.

We've collected a handful of tags from reviewers, and the
remainder of the patch set only got minimal feedback last time.
Here's what changed:

- We now use the device tree to initialize the timer driver so
it's less tighly coupled with the arch port.

- I cleaned up the defconfigs -- there's actually now just one,
and it's empty. For now I think we're OK with what the kernel
sets as defaults, but I anticipate we'll begin to expand this
as people start to use the port more.

- The VDSO symbols version is sane.

- We WFI while spinning in the boot loop.

- A handful of comments have been added.

While there are still a handful of FIXMEs in this patch set,
we've started to get enough interest from various users and
contributors that maintaining an out of tree patch set is
starting to become a big burden. Hopefully the patches are good
enough to merge now, which will at least get everyone working in
a more reasonable manner as we clean up the remaining issues.

(v8) I know it may not be the ideal time to submit a patch set right
now, as it's the middle of the merge window, but things have
calmed down quite a bit in the last month so I thought it would
be good to get everyone on the same page. There's been a handful
of changes since the last patch set, but most of them are fairly
minor:

- We changed PAGE_OFFSET to allowing mapping more physical
memory on 64-bit systems. This is user configurable, as it
triggers a different code model that generates slightly less
efficient code.

- The device tree binding documentation is back, I'd managed to
lose it at some point.

- We now pass the atomic64 test suite

- The SBI timer driver has been refactored.

(v7) It's been a while since my last patch set, but the changes han
been fairly minimal:

- The PCI cleanup patches have been dropped, we'll do them as a
separate patch set later.

- We've the Kconfig entries from CONFIG_ISA_* to
CONFIG_RISCV_ISA_*, to make grep easier.

- There have been a handful of memory model related tweaks in
I/O land, particularly relating the PCI and the upcoming
platform specification. There are significant comments in the
relevant files. This is still a WIP, but I think we're close
to getting as good as we're going to get until we end up with
some more specifications.

(v6) As it's been only a day since the v5 patch set, the changes are
pretty minimal:

- The patch set is now based on linux-next/master, which I
believe is a better base now that we're getting closer to
upstream.

- EARLY_PRINTK is no longer an option. Since the SBI console is
reasonable, there's no penalty to enabling it (and thus no
benefit to disabling it).

- The mmap syscalls were refactored a bit.

(v5) Things have really started to calm down, so this is fairly
similar to the v4 patch set. The most interesting changes
include:

- We've moved back to a single patch set.

- SMP support has been fixed, I was accidentally running on a
non-SMP configuration. There were various mistakes all over
the tree as a result of this.

- The cmpxchg syscalls have been removed, as they were deemed a
bad idea. As a result, RISC-V Linux systems mandate the A
extension. The corresponding Kconfig entry to enable builds
on non-A systems has been removed.

- A few more atomic fixes: mostly fence changes, but those
resulted in a handful of additional macros that were no
longer necessary.

- riscv_early_sie has been removed.

(v4) There have only been a few changes since the v3 patch set:

- The cmpxchg64 syscall is no longer enabled on 32-bit systems.
It's not possible to provide this on SMP systems, and it's
not necessary as glibc knows not to call it.

- We provide a ELF_HWCAP so users can determine the ISA of the
machine the kernel is running on.

- The multi-line comments are in a better form.

- There were a handful of headers that could be replaced with
the asm-generic versions, and a few unnecessary definitions.

- We no longer use printk, but instead use pr_*.

- A few Kconfig and defconfig entries have been cleaned up.

(v3) A highlight of the changes since the v2 patch set includes:

- We've split out all our drivers into separate patch sets,
which I've already sent out to the relevant maintainers. I
haven't included those patches in this patch set, but some of
them are necessary to build our port.

- The patch set is now split up differently: rather than being
split per directory it is split per topic. Hopefully this
will make it easier to review the port on the mailing list.
The split is a bit rough, so you probably still want to look
at the patch set as a whole.

- atomic.h has been completely rewritten and is hopefully now
correct. I've attempted to sanitize the various other memory
model related code as well, and I think it should all be sane
now aside from a handful of FIXMEs commented in the code.

- We've changed the cmpexchg syscall to always exist and to not
be multiplexed. There is also a VDSO entry for compare and
exchange, which allows kernels with the A extension to
execute user code without the A extension reasonably fast.

- Our user-visible register state now contains enough space for
the Q extension for 128-bit floating point, as well as a few
words to allow extensibility to future ISA extensions like
the eventual V extension for vectors.

- A handful of driver cleanups, but these have been split into
separate patch sets now so I won't duplicate them here.

(v2) A highlight of the changes since the v1 patch set includes:

- We've split out our drivers into the right places, which
means now there's a lot more patches. I'll be submitting
these patches to various subsystem maintainers and including
them in any future RISC-V patch sets until they've been
merged.

- The SBI console driver has been completely rewritten to use
the HVC helpers and is now significantly smaller.

- We've begun to use weaker barriers as opposed to just the big
"fence". There's still some work to do here, specifically:
- We need fences in the relaxed MMIO functions.
- The non-relaxed MMIO functions are missing R/W bits on their fences.
- Many AMOs need the aq and rl bits set.

- We now have thread_info in task_struct. As a result, sscratch
now contains TP instead of SP. This was necessary because
thread_info is no longer on the stack.

- A few shared routines have been added that we use instead of
creating another arch copy"

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

* tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux:
RISC-V: Build Infrastructure
RISC-V: User-facing API
RISC-V: Paging and MMU
RISC-V: Device, timer, IRQs, and the SBI
RISC-V: Task implementation
RISC-V: ELF and module implementation
RISC-V: Generic library routines and assembly
RISC-V: Atomic and Locking Code
RISC-V: Init and Halt Code
dt-bindings: RISC-V CPU Bindings
lib: Add shared copies of some GCC library routines
MAINTAINERS: Add RISC-V

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Revision tags: v4.14, v4.13.5, v4.13
# fab957c1 10-Jul-2017 Palmer Dabbelt <palmer@dabbelt.com>

RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V
memory model. While this code corforms to the current RISC-V ISA
specifications (user 2.2 and pri

RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V
memory model. While this code corforms to the current RISC-V ISA
specifications (user 2.2 and priv 1.10), the memory model is somewhat
underspecified in those documents. There is a working group that hopes
to produce a formal memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>

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