Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
[ARM] 5300/1: fixup spitz reset during boot
[ARM]

Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
[ARM] 5300/1: fixup spitz reset during boot
[ARM] 5295/1: make ZONE_DMA optional
[ARM] 5239/1: Palm Zire 72 power management support
[ARM] 5298/1: Drop desc_handle_irq()
[ARM] 5297/1: [KS8695] Fix two compile-time warnings
[ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
[ARM] pxa: allow multi-machine PCMCIA builds
[ARM] pxa: add preliminary CPUFREQ support for PXA3xx
[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
[ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
[ARM] pxa/zylonite: add support for USB OHCI
[ARM] ohci-pxa27x: use ioremap() and offset for register access
[ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
[ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
[ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
[ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
[ARM] pxa: simplify DMA register definitions
[ARM] pxa: make additional DCSR bits valid for PXA3xx
[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
...

Fixed up conflicts in
arch/arm/mach-versatile/core.c
sound/soc/pxa/pxa2xx-ac97.c
sound/soc/pxa/pxa2xx-i2s.c
manually.

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Merge branches 'machtypes', 'core', 'ep93xx', 'ks8695', 'netdev' and 'sa1100' into devel

[ARM] Convert asm/uaccess.h to linux/uaccess.h

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Merge branch 'master' of /home/sam/kernel/linux-2.6/

Merge branch 'master' of /home/trondmy/kernel/linux-2.6/

Merge rsync://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

Conflicts:

include/linux/kernel.h

Merge branch 'genirq' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'genirq' of master.kernel.org:/home/rmk/linux-2.6-arm: (24 commits)
[ARM] 3683/2: ARM: Convert at91rm9200 to generic irq handl

Merge branch 'genirq' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'genirq' of master.kernel.org:/home/rmk/linux-2.6-arm: (24 commits)
[ARM] 3683/2: ARM: Convert at91rm9200 to generic irq handling
[ARM] 3682/2: ARM: Convert ixp4xx to generic irq handling
[ARM] 3702/1: ARM: Convert ixp23xx to generic irq handling
[ARM] 3701/1: ARM: Convert plat-omap to generic irq handling
[ARM] 3700/1: ARM: Convert lh7a40x to generic irq handling
[ARM] 3699/1: ARM: Convert s3c2410 to generic irq handling
[ARM] 3698/1: ARM: Convert sa1100 to generic irq handling
[ARM] 3697/1: ARM: Convert shark to generic irq handling
[ARM] 3696/1: ARM: Convert clps711x to generic irq handling
[ARM] 3694/1: ARM: Convert ecard driver to generic irq handling
[ARM] 3693/1: ARM: Convert omap1 to generic irq handling
[ARM] 3691/1: ARM: Convert imx to generic irq handling
[ARM] 3688/1: ARM: Convert clps7500 to generic irq handling
[ARM] 3687/1: ARM: Convert integrator to generic irq handling
[ARM] 3685/1: ARM: Convert pxa to generic irq handling
[ARM] 3684/1: ARM: Convert l7200 to generic irq handling
[ARM] 3681/1: ARM: Convert ixp2000 to generic irq handling
[ARM] 3680/1: ARM: Convert footbridge to generic irq handling
[ARM] 3695/1: ARM drivers/pcmcia: Fixup includes
[ARM] 3689/1: ARM drivers/input/touchscreen: Fixup includes
...

Manual conflict resolved in kernel/irq/handle.c (butt-ugly ARM tickless
code).

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[ARM] 3692/1: ARM: coswitch irq handling to the generic implementation

Patch from Thomas Gleixner

From: Thomas Gleixner <tglx@linutronix.de>

Switch the ARM irq core handling to the generic impleme

[ARM] 3692/1: ARM: coswitch irq handling to the generic implementation

Patch from Thomas Gleixner

From: Thomas Gleixner <tglx@linutronix.de>

Switch the ARM irq core handling to the generic implementation. The
ARM specific header files now contain mostly migration stubs and
helper macros. Note that each machine type must be converted after
this step seperately. This was seperated out from the patch for easier
review.

The main changes for the machine type code is the conversion of the
type handlers to a 'type flow' and 'chip' model. This affects only the
multiplex interrupt handlers. A conversion macro needs to be added to
those implementations, which defines the data structure which is
registered by the set_irq_chained_handler() macro.

Some minor fixups of include files and the conversion of data
structure access is necessary all over the place.

The mostly macro based conversion was provided to allow an easy
migration of the existing implementations.

The code compiles on all defconfigs available in arch/arm/configs
except those which were broken also before applying the conversion
patches.

The code has been boot and runtime tested on most ARM platforms. The
results of an extensive testing and bugfixing series can be found
at: http://www.linutronix.de/index.php?page=testing

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Pull release into acpica branch

Merge with /home/shaggy/git/linus-clean/

Merge branch 'master' of /usr/src/ntfs-2.6/

Merge branch 'upstream'

Merge branch 'upstream'

Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git

Signed-off-by: Steve French <sfrench@us.ibm.com>

Merge master.kernel.org:/home/rmk/linux-2.6-arm

[ARM] 3256/1: Make the function-returning ldm's use sp as the base register

Patch from Catalin Marinas

If the low interrupt latency mode is enabled for the CPU (from ARMv6
onwards), the ldm/stm ins

[ARM] 3256/1: Make the function-returning ldm's use sp as the base register

Patch from Catalin Marinas

If the low interrupt latency mode is enabled for the CPU (from ARMv6
onwards), the ldm/stm instructions are no longer atomic. An ldm instruction
restoring the sp and pc registers can be interrupted immediately after sp
was updated but before the pc. If this happens, the CPU restores the base
register to the value before the ldm instruction but if the base register
is not sp, the interrupt routine will corrupt the stack and the restarted
ldm instruction will load garbage.

Note that future ARM cores might always run in the low interrupt latency
mode.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Linux-2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in

Linux-2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

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