| w83c553f.h (012771d88adfb5e0886591880041f05fc8b15bdd) | w83c553f.h (6d0f6bcf337c5261c08fabe12982178c2c489d76) |
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| 1/* 2 * (C) Copyright 2000 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or --- 59 unchanged lines hidden (view full) --- 68#define IDECSR_P0F16 0x02 69#define IDECSR_P1EN 0x10 70#define IDECSR_P1F16 0x20 71#define IDECSR_LEGIRQ 0x800 72 73/* 74 * Interrupt controller 75 */ | 1/* 2 * (C) Copyright 2000 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or --- 59 unchanged lines hidden (view full) --- 68#define IDECSR_P0F16 0x02 69#define IDECSR_P1EN 0x10 70#define IDECSR_P1F16 0x20 71#define IDECSR_LEGIRQ 0x800 72 73/* 74 * Interrupt controller 75 */ |
| 76#define W83C553F_PIC1_ICW1 CFG_ISA_IO + 0x20 77#define W83C553F_PIC1_ICW2 CFG_ISA_IO + 0x21 78#define W83C553F_PIC1_ICW3 CFG_ISA_IO + 0x21 79#define W83C553F_PIC1_ICW4 CFG_ISA_IO + 0x21 80#define W83C553F_PIC1_OCW1 CFG_ISA_IO + 0x21 81#define W83C553F_PIC1_OCW2 CFG_ISA_IO + 0x20 82#define W83C553F_PIC1_OCW3 CFG_ISA_IO + 0x20 83#define W83C553F_PIC1_ELC CFG_ISA_IO + 0x4D0 84#define W83C553F_PIC2_ICW1 CFG_ISA_IO + 0xA0 85#define W83C553F_PIC2_ICW2 CFG_ISA_IO + 0xA1 86#define W83C553F_PIC2_ICW3 CFG_ISA_IO + 0xA1 87#define W83C553F_PIC2_ICW4 CFG_ISA_IO + 0xA1 88#define W83C553F_PIC2_OCW1 CFG_ISA_IO + 0xA1 89#define W83C553F_PIC2_OCW2 CFG_ISA_IO + 0xA0 90#define W83C553F_PIC2_OCW3 CFG_ISA_IO + 0xA0 91#define W83C553F_PIC2_ELC CFG_ISA_IO + 0x4D1 | 76#define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20 77#define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21 78#define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21 79#define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21 80#define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21 81#define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20 82#define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20 83#define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0 84#define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0 85#define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1 86#define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1 87#define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1 88#define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1 89#define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0 90#define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0 91#define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1 |
| 92 | 92 |
| 93#define W83C553F_TMR1_CMOD CFG_ISA_IO + 0x43 | 93#define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43 |
| 94 95/* 96 * DMA controller 97 */ | 94 95/* 96 * DMA controller 97 */ |
| 98#define W83C553F_DMA1 CFG_ISA_IO + 0x000 /* channel 0 - 3 */ 99#define W83C553F_DMA2 CFG_ISA_IO + 0x0C0 /* channel 4 - 7 */ | 98#define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */ 99#define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */ |
| 100 101/* command/status register bit definitions */ 102 103#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ 104#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ 105#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ 106#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ 107 --- 71 unchanged lines hidden --- | 100 101/* command/status register bit definitions */ 102 103#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ 104#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ 105#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ 106#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ 107 --- 71 unchanged lines hidden --- |