tsec.h (a32a6be28fbbec19b6581609844ca3ec313b9d81) tsec.h (063c12633d5ad74d52152d9c358e715475e17629)
1/*
2 * tsec.h
3 *
4 * Driver for the Motorola Triple Speed Ethernet Controller
5 *
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
8 * herein by reference.

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14 *
15 */
16
17#ifndef __TSEC_H
18#define __TSEC_H
19
20#include <net.h>
21#include <config.h>
1/*
2 * tsec.h
3 *
4 * Driver for the Motorola Triple Speed Ethernet Controller
5 *
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
8 * herein by reference.

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14 *
15 */
16
17#ifndef __TSEC_H
18#define __TSEC_H
19
20#include <net.h>
21#include <config.h>
22#include <phy.h>
23#include <asm/fsl_enet.h>
22
23#define TSEC_SIZE 0x01000
24#define TSEC_MDIO_OFFSET 0x01000
25
24
25#define TSEC_SIZE 0x01000
26#define TSEC_MDIO_OFFSET 0x01000
27
28#define CONFIG_SYS_MDIO_BASE_ADDR (TSEC_BASE_ADDR + 0x520)
29
30#define DEFAULT_MII_NAME "FSL_MDIO"
31
26#define STD_TSEC_INFO(num) \
27{ \
28 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
32#define STD_TSEC_INFO(num) \
33{ \
34 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
29 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
30 .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
35 .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
31 + (num - 1) * TSEC_MDIO_OFFSET), \
32 .devname = CONFIG_TSEC##num##_NAME, \
33 .phyaddr = TSEC##num##_PHY_ADDR, \
36 + (num - 1) * TSEC_MDIO_OFFSET), \
37 .devname = CONFIG_TSEC##num##_NAME, \
38 .phyaddr = TSEC##num##_PHY_ADDR, \
34 .flags = TSEC##num##_FLAGS \
39 .flags = TSEC##num##_FLAGS, \
40 .mii_devname = DEFAULT_MII_NAME \
35}
36
37#define SET_STD_TSEC_INFO(x, num) \
38{ \
39 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
41}
42
43#define SET_STD_TSEC_INFO(x, num) \
44{ \
45 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
40 x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
41 x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
46 x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
42 + (num - 1) * TSEC_MDIO_OFFSET); \
43 x.devname = CONFIG_TSEC##num##_NAME; \
44 x.phyaddr = TSEC##num##_PHY_ADDR; \
45 x.flags = TSEC##num##_FLAGS;\
47 + (num - 1) * TSEC_MDIO_OFFSET); \
48 x.devname = CONFIG_TSEC##num##_NAME; \
49 x.phyaddr = TSEC##num##_PHY_ADDR; \
50 x.flags = TSEC##num##_FLAGS;\
51 x.mii_devname = DEFAULT_MII_NAME;\
46}
47
48#define MAC_ADDR_LEN 6
49
50/* #define TSEC_TIMEOUT 1000000 */
51#define TSEC_TIMEOUT 1000
52#define TOUT_LOOP 1000000
53
52}
53
54#define MAC_ADDR_LEN 6
55
56/* #define TSEC_TIMEOUT 1000000 */
57#define TSEC_TIMEOUT 1000
58#define TOUT_LOOP 1000000
59
54#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
55
56/* TBI register addresses */
57#define TBI_CR 0x00
58#define TBI_SR 0x01
59#define TBI_ANA 0x04
60#define TBI_ANLPBPA 0x05
61#define TBI_ANEX 0x06
62#define TBI_TBICON 0x11
63

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91#define MACCFG2_INIT_SETTINGS 0x00007205
92#define MACCFG2_FULL_DUPLEX 0x00000001
93#define MACCFG2_IF 0x00000300
94#define MACCFG2_GMII 0x00000200
95#define MACCFG2_MII 0x00000100
96
97#define ECNTRL_INIT_SETTINGS 0x00001000
98#define ECNTRL_TBI_MODE 0x00000020
60/* TBI register addresses */
61#define TBI_CR 0x00
62#define TBI_SR 0x01
63#define TBI_ANA 0x04
64#define TBI_ANLPBPA 0x05
65#define TBI_ANEX 0x06
66#define TBI_TBICON 0x11
67

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95#define MACCFG2_INIT_SETTINGS 0x00007205
96#define MACCFG2_FULL_DUPLEX 0x00000001
97#define MACCFG2_IF 0x00000300
98#define MACCFG2_GMII 0x00000200
99#define MACCFG2_MII 0x00000100
100
101#define ECNTRL_INIT_SETTINGS 0x00001000
102#define ECNTRL_TBI_MODE 0x00000020
103#define ECNTRL_REDUCED_MODE 0x00000010
99#define ECNTRL_R100 0x00000008
104#define ECNTRL_R100 0x00000008
105#define ECNTRL_REDUCED_MII_MODE 0x00000004
100#define ECNTRL_SGMII_MODE 0x00000002
101
106#define ECNTRL_SGMII_MODE 0x00000002
107
102#define miim_end -2
103#define miim_read -1
104
105#ifndef CONFIG_SYS_TBIPA_VALUE
106 #define CONFIG_SYS_TBIPA_VALUE 0x1f
107#endif
108#ifndef CONFIG_SYS_TBIPA_VALUE
109 #define CONFIG_SYS_TBIPA_VALUE 0x1f
110#endif
108#define MIIMCFG_INIT_VALUE 0x00000003
109#define MIIMCFG_RESET 0x80000000
110
111
111#define MIIMIND_BUSY 0x00000001
112#define MIIMIND_NOTVALID 0x00000004
113
114#define MIIM_CONTROL 0x00
115#define MIIM_CONTROL_RESET 0x00009140
116#define MIIM_CONTROL_INIT 0x00001140
117#define MIIM_CONTROL_RESTART 0x00001340
118#define MIIM_ANEN 0x00001000
119
120#define MIIM_CR 0x00
121#define MIIM_CR_RST 0x00008000
122#define MIIM_CR_INIT 0x00001000
123
124#define MIIM_STATUS 0x1
125#define MIIM_STATUS_AN_DONE 0x00000020
126#define MIIM_STATUS_LINK 0x0004
127
128#define MIIM_PHYIR1 0x2
129#define MIIM_PHYIR2 0x3
130
131#define MIIM_ANAR 0x4
132#define MIIM_ANAR_INIT 0x1e1
133
134#define MIIM_TBI_ANLPBPA 0x5
135#define MIIM_TBI_ANLPBPA_HALF 0x00000040
136#define MIIM_TBI_ANLPBPA_FULL 0x00000020
137
138#define MIIM_TBI_ANEX 0x6
139#define MIIM_TBI_ANEX_NP 0x00000004
140#define MIIM_TBI_ANEX_PRX 0x00000002
141
142#define MIIM_GBIT_CONTROL 0x9
143#define MIIM_GBIT_CONTROL_INIT 0xe00
144
145#define MIIM_EXT_PAGE_ACCESS 0x1f
146
147/* Broadcom BCM54xx -- taken from linux sungem_phy */
148#define MIIM_BCM54xx_AUXCNTL 0x18
149#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7)
150#define MIIM_BCM54xx_AUXSTATUS 0x19
151#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
152#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
153
154#define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
155#define MIIM_BCM54XX_SHD_WRITE 0x8000
156#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
157#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
158#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
159 (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
160 MIIM_BCM54XX_SHD_DATA(data))
161
162#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
163#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
164#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
165#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
166
167/* Cicada Auxiliary Control/Status Register */
168#define MIIM_CIS8201_AUX_CONSTAT 0x1c
169#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
170#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
171#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
172#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
173#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
174
175/* Cicada Extended Control Register 1 */
176#define MIIM_CIS8201_EXT_CON1 0x17
177#define MIIM_CIS8201_EXTCON1_INIT 0x0000
178
179/* Cicada 8204 Extended PHY Control Register 1 */
180#define MIIM_CIS8204_EPHY_CON 0x17
181#define MIIM_CIS8204_EPHYCON_INIT 0x0006
182#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
183
184/* Cicada 8204 Serial LED Control Register */
185#define MIIM_CIS8204_SLED_CON 0x1b
186#define MIIM_CIS8204_SLEDCON_INIT 0x1115
187
188#define MIIM_GBIT_CON 0x09
189#define MIIM_GBIT_CON_ADVERT 0x0e00
190
191/* Entry for Vitesse VSC8244 regs starts here */
192/* Vitesse VSC8244 Auxiliary Control/Status Register */
193#define MIIM_VSC8244_AUX_CONSTAT 0x1c
194#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
195#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
196#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
197#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
198#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
199#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
200
201/* Vitesse VSC8244 Extended PHY Control Register 1 */
202#define MIIM_VSC8244_EPHY_CON 0x17
203#define MIIM_VSC8244_EPHYCON_INIT 0x0006
204
205/* Vitesse VSC8244 Serial LED Control Register */
206#define MIIM_VSC8244_LED_CON 0x1b
207#define MIIM_VSC8244_LEDCON_INIT 0xF011
208
209/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
210/* Vitesse VSC8601 Extended PHY Control Register 1 */
211#define MIIM_VSC8601_EPHY_CON 0x17
212#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
213#define MIIM_VSC8601_SKEW_CTRL 0x1c
214
215/* 88E1011 PHY Status Register */
216#define MIIM_88E1011_PHY_STATUS 0x11
217#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
218#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
219#define MIIM_88E1011_PHYSTAT_100 0x4000
220#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
221#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
222#define MIIM_88E1011_PHYSTAT_LINK 0x0400
223
224#define MIIM_88E1011_PHY_SCR 0x10
225#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
226
227/* 88E1111 PHY LED Control Register */
228#define MIIM_88E1111_PHY_LED_CONTROL 24
229#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
230#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
231
232/* 88E1121 PHY LED Control Register */
233#define MIIM_88E1121_PHY_LED_CTRL 16
234#define MIIM_88E1121_PHY_LED_PAGE 3
235#define MIIM_88E1121_PHY_LED_DEF 0x0030
236
237/* 88E1121 PHY IRQ Enable/Status Register */
238#define MIIM_88E1121_PHY_IRQ_EN 18
239#define MIIM_88E1121_PHY_IRQ_STATUS 19
240
241#define MIIM_88E1121_PHY_PAGE 22
242
243/* 88E1145 Extended PHY Specific Control Register */
244#define MIIM_88E1145_PHY_EXT_CR 20
245#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
246#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
247
248#define MIIM_88E1145_PHY_PAGE 29
249#define MIIM_88E1145_PHY_CAL_OV 30
250
251/* RTL8211B PHY Status Register */
252#define MIIM_RTL8211B_PHY_STATUS 0x11
253#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
254#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
255#define MIIM_RTL8211B_PHYSTAT_100 0x4000
256#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
257#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
258#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
259
260/* DM9161 Control register values */
261#define MIIM_DM9161_CR_STOP 0x0400
262#define MIIM_DM9161_CR_RSTAN 0x1200
263
264#define MIIM_DM9161_SCR 0x10
265#define MIIM_DM9161_SCR_INIT 0x0610
266
267/* DM9161 Specified Configuration and Status Register */
268#define MIIM_DM9161_SCSR 0x11
269#define MIIM_DM9161_SCSR_100F 0x8000
270#define MIIM_DM9161_SCSR_100H 0x4000
271#define MIIM_DM9161_SCSR_10F 0x2000
272#define MIIM_DM9161_SCSR_10H 0x1000
273
274/* DM9161 10BT Configuration/Status */
275#define MIIM_DM9161_10BTCSR 0x12
276#define MIIM_DM9161_10BTCSR_INIT 0x7800
277
278/* LXT971 Status 2 registers */
279#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
280#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
281#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
282#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
283#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
284#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
285
286/* DP83865 Control register values */
287#define MIIM_DP83865_CR_INIT 0x9200
288
289/* DP83865 Link and Auto-Neg Status Register */
290#define MIIM_DP83865_LANR 0x11
291#define MIIM_DP83865_SPD_MASK 0x0018
292#define MIIM_DP83865_SPD_1000 0x0010
293#define MIIM_DP83865_SPD_100 0x0008
294#define MIIM_DP83865_DPX_FULL 0x0002
295
296#define MIIM_READ_COMMAND 0x00000001
297
298#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
299
300#define MINFLR_INIT_SETTINGS 0x00000040
301
302#define DMACTRL_INIT_SETTINGS 0x000000c3
303#define DMACTRL_GRS 0x00000010
304#define DMACTRL_GTS 0x00000008
305

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462 uint gaddr3; /* Group Address Register 3 */
463 uint gaddr4; /* Group Address Register 4 */
464 uint gaddr5; /* Group Address Register 5 */
465 uint gaddr6; /* Group Address Register 6 */
466 uint gaddr7; /* Group Address Register 7 */
467 uint res2[24];
468} tsec_hash_t;
469
112#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
113
114#define MINFLR_INIT_SETTINGS 0x00000040
115
116#define DMACTRL_INIT_SETTINGS 0x000000c3
117#define DMACTRL_GRS 0x00000010
118#define DMACTRL_GTS 0x00000008
119

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276 uint gaddr3; /* Group Address Register 3 */
277 uint gaddr4; /* Group Address Register 4 */
278 uint gaddr5; /* Group Address Register 5 */
279 uint gaddr6; /* Group Address Register 6 */
280 uint gaddr7; /* Group Address Register 7 */
281 uint res2[24];
282} tsec_hash_t;
283
470typedef struct tsec_mdio {
471 uint res1[4];
472 uint ieventm;
473 uint imaskm;
474 uint res2;
475 uint emapm;
476 uint res3[320];
477 uint miimcfg; /* MII Management: Configuration */
478 uint miimcom; /* MII Management: Command */
479 uint miimadd; /* MII Management: Address */
480 uint miimcon; /* MII Management: Control */
481 uint miimstat; /* MII Management: Status */
482 uint miimind; /* MII Management: Indicators */
483 uint res4[690];
484} tsec_mdio_t;
485
486typedef struct tsec
487{
488 /* General Control and Status Registers (0x2_n000) */
489 uint res000[4];
490
491 uint ievent; /* Interrupt Event */
492 uint imask; /* Interrupt Mask */
493 uint edis; /* Error Disabled */

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573 uint resb00[62];
574 uint attr; /* Default Attribute Register */
575 uint attreli; /* Default Attribute Extract Length and Index */
576
577 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
578 uint resc00[256];
579} tsec_t;
580
284typedef struct tsec
285{
286 /* General Control and Status Registers (0x2_n000) */
287 uint res000[4];
288
289 uint ievent; /* Interrupt Event */
290 uint imask; /* Interrupt Mask */
291 uint edis; /* Error Disabled */

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371 uint resb00[62];
372 uint attr; /* Default Attribute Register */
373 uint attreli; /* Default Attribute Extract Length and Index */
374
375 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
376 uint resc00[256];
377} tsec_t;
378
581#define TSEC_GIGABIT (1)
379#define TSEC_GIGABIT (1 << 0)
582
380
583/* This flag currently only has
584 * meaning if we're using the eTSEC */
381/* These flags currently only have meaning if we're using the eTSEC */
585#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
586#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
382#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
383#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
587#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */
588
589struct tsec_private {
590 tsec_t *regs;
384
385struct tsec_private {
386 tsec_t *regs;
591 tsec_mdio_t *phyregs;
592 tsec_mdio_t *phyregs_sgmii;
593 struct phy_info *phyinfo;
387 struct tsec_mii_mng *phyregs_sgmii;
388 struct phy_device *phydev;
389 phy_interface_t interface;
390 struct mii_dev *bus;
594 uint phyaddr;
391 uint phyaddr;
392 char mii_devname[16];
595 u32 flags;
393 u32 flags;
596 uint link;
597 uint duplexity;
598 uint speed;
599};
600
394};
395
601
602/*
603 * struct phy_cmd: A command for reading or writing a PHY register
604 *
605 * mii_reg: The register to read or write
606 *
607 * mii_data: For writes, the value to put in the register.
608 * A value of -1 indicates this is a read.
609 *
610 * funct: A function pointer which is invoked for each command.
611 * For reads, this function will be passed the value read
612 * from the PHY, and process it.
613 * For writes, the result of this function will be written
614 * to the PHY register
615 */
616struct phy_cmd {
617 uint mii_reg;
618 uint mii_data;
619 uint (*funct) (uint mii_reg, struct tsec_private * priv);
620};
621
622/* struct phy_info: a structure which defines attributes for a PHY
623 *
624 * id will contain a number which represents the PHY. During
625 * startup, the driver will poll the PHY to find out what its
626 * UID--as defined by registers 2 and 3--is. The 32-bit result
627 * gotten from the PHY will be shifted right by "shift" bits to
628 * discard any bits which may change based on revision numbers
629 * unimportant to functionality
630 *
631 * The struct phy_cmd entries represent pointers to an arrays of
632 * commands which tell the driver what to do to the PHY.
633 */
634struct phy_info {
635 uint id;
636 char *name;
637 uint shift;
638 /* Called to configure the PHY, and modify the controller
639 * based on the results */
640 struct phy_cmd *config;
641
642 /* Called when starting up the controller */
643 struct phy_cmd *startup;
644
645 /* Called when bringing down the controller */
646 struct phy_cmd *shutdown;
647};
648
649struct tsec_info_struct {
650 tsec_t *regs;
396struct tsec_info_struct {
397 tsec_t *regs;
651 tsec_mdio_t *miiregs;
652 tsec_mdio_t *miiregs_sgmii;
398 struct tsec_mii_mng *miiregs_sgmii;
653 char *devname;
399 char *devname;
400 char *mii_devname;
401 phy_interface_t interface;
654 unsigned int phyaddr;
655 u32 flags;
656};
657
658int tsec_standard_init(bd_t *bis);
659int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
660
661#endif /* __TSEC_H */
402 unsigned int phyaddr;
403 u32 flags;
404};
405
406int tsec_standard_init(bd_t *bis);
407int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
408
409#endif /* __TSEC_H */