tsec.h (56a27a1e6cbc414a8d5b9e59314119777c092635) tsec.h (9a1d6af55ecd73938d49076422e87da9f87fc68f)
1/*
2 * tsec.h
3 *
4 * Driver for the Motorola Triple Speed Ethernet Controller
5 *
6 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
7 * (C) Copyright 2003, Motorola, Inc.
8 * maintained by Xianghua Xiao (x.xiao@motorola.com)

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13
14#ifndef __TSEC_H
15#define __TSEC_H
16
17#include <net.h>
18#include <config.h>
19#include <phy.h>
20
1/*
2 * tsec.h
3 *
4 * Driver for the Motorola Triple Speed Ethernet Controller
5 *
6 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
7 * (C) Copyright 2003, Motorola, Inc.
8 * maintained by Xianghua Xiao (x.xiao@motorola.com)

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13
14#ifndef __TSEC_H
15#define __TSEC_H
16
17#include <net.h>
18#include <config.h>
19#include <phy.h>
20
21#ifndef CONFIG_DM_ETH
22
21#ifdef CONFIG_LS102XA
22#define TSEC_SIZE 0x40000
23#define TSEC_MDIO_OFFSET 0x40000
24#else
25#define TSEC_SIZE 0x01000
26#define TSEC_MDIO_OFFSET 0x01000
27#endif
28

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59 x.regs = TSEC_GET_REGS_BASE(num); \
60 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
61 x.devname = CONFIG_TSEC##num##_NAME; \
62 x.phyaddr = TSEC##num##_PHY_ADDR; \
63 x.flags = TSEC##num##_FLAGS;\
64 x.mii_devname = DEFAULT_MII_NAME;\
65}
66
23#ifdef CONFIG_LS102XA
24#define TSEC_SIZE 0x40000
25#define TSEC_MDIO_OFFSET 0x40000
26#else
27#define TSEC_SIZE 0x01000
28#define TSEC_MDIO_OFFSET 0x01000
29#endif
30

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61 x.regs = TSEC_GET_REGS_BASE(num); \
62 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
63 x.devname = CONFIG_TSEC##num##_NAME; \
64 x.phyaddr = TSEC##num##_PHY_ADDR; \
65 x.flags = TSEC##num##_FLAGS;\
66 x.mii_devname = DEFAULT_MII_NAME;\
67}
68
69#endif /* CONFIG_DM_ETH */
70
67#define MAC_ADDR_LEN 6
68
69/* #define TSEC_TIMEOUT 1000000 */
70#define TSEC_TIMEOUT 1000
71#define TOUT_LOOP 1000000
72
73/* TBI register addresses */
74#define TBI_CR 0x00

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397 struct phy_device *phydev;
398 phy_interface_t interface;
399 struct mii_dev *bus;
400 uint phyaddr;
401 char mii_devname[16];
402 u32 flags;
403 uint rx_idx; /* index of the current RX buffer */
404 uint tx_idx; /* index of the current TX buffer */
71#define MAC_ADDR_LEN 6
72
73/* #define TSEC_TIMEOUT 1000000 */
74#define TSEC_TIMEOUT 1000
75#define TOUT_LOOP 1000000
76
77/* TBI register addresses */
78#define TBI_CR 0x00

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401 struct phy_device *phydev;
402 phy_interface_t interface;
403 struct mii_dev *bus;
404 uint phyaddr;
405 char mii_devname[16];
406 u32 flags;
407 uint rx_idx; /* index of the current RX buffer */
408 uint tx_idx; /* index of the current TX buffer */
409#ifndef CONFIG_DM_ETH
405 struct eth_device *dev;
410 struct eth_device *dev;
411#else
412 struct udevice *dev;
413#endif
406};
407
408struct tsec_info_struct {
409 struct tsec __iomem *regs;
410 struct tsec_mii_mng __iomem *miiregs_sgmii;
411 char *devname;
412 char *mii_devname;
413 phy_interface_t interface;
414 unsigned int phyaddr;
415 u32 flags;
416};
417
414};
415
416struct tsec_info_struct {
417 struct tsec __iomem *regs;
418 struct tsec_mii_mng __iomem *miiregs_sgmii;
419 char *devname;
420 char *mii_devname;
421 phy_interface_t interface;
422 unsigned int phyaddr;
423 u32 flags;
424};
425
426#ifndef CONFIG_DM_ETH
418int tsec_standard_init(bd_t *bis);
419int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
427int tsec_standard_init(bd_t *bis);
428int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
429#endif
420
421#endif /* __TSEC_H */
430
431#endif /* __TSEC_H */