| ns87308.h (e85390dc1d9c3c942c11bbf003e6c10a73e25ed6) | ns87308.h (6d0f6bcf337c5261c08fabe12982178c2c489d76) |
|---|---|
| 1/* 2 * (C) Copyright 2000 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or --- 60 unchanged lines hidden (view full) --- 69 70#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */ 71#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */ 72#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */ 73#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */ 74#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */ 75#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */ 76 | 1/* 2 * (C) Copyright 2000 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or --- 60 unchanged lines hidden (view full) --- 69 70#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */ 71#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */ 72#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */ 73#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */ 74#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */ 75#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */ 76 |
| 77#if defined(CFG_NS87308_BADDR_0x) 78#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x) 79#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_0x) 80#elif defined(CFG_NS87308_BADDR_10) 81#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10) 82#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_10) 83#elif defined(CFG_NS87308_BADDR_11) 84#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11) 85#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_11) | 77#if defined(CONFIG_SYS_NS87308_BADDR_0x) 78#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x) 79#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x) 80#elif defined(CONFIG_SYS_NS87308_BADDR_10) 81#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10) 82#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10) 83#elif defined(CONFIG_SYS_NS87308_BADDR_11) 84#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11) 85#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11) |
| 86#endif 87 88/* PnP register definitions */ 89 90#define SET_RD_DATA_PORT 0x00 91#define SERIAL_ISOLATION 0x01 92#define CONFIG_CONTROL 0x02 93#define WAKE_CSN 0x03 --- 33 unchanged lines hidden (view full) --- 127#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/ 128#define LDEV_FDC 0x03 /*floppy disk controller*/ 129#define LDEV_PARP 0x04 /*Parallel port*/ 130#define LDEV_UART2 0x05 131#define LDEV_UART1 0x06 132#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/ 133#define LDEV_POWRMAN 0x08 /*Power Managment*/ 134 | 86#endif 87 88/* PnP register definitions */ 89 90#define SET_RD_DATA_PORT 0x00 91#define SERIAL_ISOLATION 0x01 92#define CONFIG_CONTROL 0x02 93#define WAKE_CSN 0x03 --- 33 unchanged lines hidden (view full) --- 127#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/ 128#define LDEV_FDC 0x03 /*floppy disk controller*/ 129#define LDEV_PARP 0x04 /*Parallel port*/ 130#define LDEV_UART2 0x05 131#define LDEV_UART1 0x06 132#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/ 133#define LDEV_POWRMAN 0x08 /*Power Managment*/ 134 |
| 135#define CFG_NS87308_KBC1 (1 << LDEV_KBC1) 136#define CFG_NS87308_KBC2 (1 << LDEV_KBC2) 137#define CFG_NS87308_MOUSE (1 << LDEV_MOUSE) 138#define CFG_NS87308_RTC_APC (1 << LDEV_RTC_APC) 139#define CFG_NS87308_FDC (1 << LDEV_FDC) 140#define CFG_NS87308_PARP (1 << LDEV_PARP) 141#define CFG_NS87308_UART2 (1 << LDEV_UART2) 142#define CFG_NS87308_UART1 (1 << LDEV_UART1) 143#define CFG_NS87308_GPIO (1 << LDEV_GPIO) 144#define CFG_NS87308_POWRMAN (1 << LDEV_POWRMAN) | 135#define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1) 136#define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2) 137#define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE) 138#define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC) 139#define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC) 140#define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP) 141#define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2) 142#define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1) 143#define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO) 144#define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN) |
| 145 146/*some functions and macro's for doing configuration */ 147 148static inline void read_pnp_config(unsigned char index, unsigned char *data) 149{ 150 pci_writeb(index,IO_INDEX); 151 pci_readb(IO_DATA, *data); 152} --- 6 unchanged lines hidden (view full) --- 159 160static inline void pnp_set_device(unsigned char dev) 161{ 162 write_pnp_config(LOGICAL_DEVICE, dev); 163} 164 165static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data) 166{ | 145 146/*some functions and macro's for doing configuration */ 147 148static inline void read_pnp_config(unsigned char index, unsigned char *data) 149{ 150 pci_writeb(index,IO_INDEX); 151 pci_readb(IO_DATA, *data); 152} --- 6 unchanged lines hidden (view full) --- 159 160static inline void pnp_set_device(unsigned char dev) 161{ 162 write_pnp_config(LOGICAL_DEVICE, dev); 163} 164 165static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data) 166{ |
| 167 pci_writeb(index, CFG_ISA_IO + base); | 167 pci_writeb(index, CONFIG_SYS_ISA_IO + base); |
| 168 eieio(); | 168 eieio(); |
| 169 pci_writeb(data, CFG_ISA_IO + base + 1); | 169 pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1); |
| 170} 171 172/*void write_pnp_config(unsigned char index, unsigned char data); 173void pnp_set_device(unsigned char dev); 174*/ 175 176#define PNP_SET_DEVICE_BASE(dev,base) \ 177 pnp_set_device(dev); \ --- 45 unchanged lines hidden (view full) --- 223#define MCR_MDSL_CIR 0x06 /*Consumer IR*/ 224 225#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */ 226#define FCR_TXFTH1 0x20 /* for interrupt trigger */ 227 228/* 229 * Default NS87308 configuration 230 */ | 170} 171 172/*void write_pnp_config(unsigned char index, unsigned char data); 173void pnp_set_device(unsigned char dev); 174*/ 175 176#define PNP_SET_DEVICE_BASE(dev,base) \ 177 pnp_set_device(dev); \ --- 45 unchanged lines hidden (view full) --- 223#define MCR_MDSL_CIR 0x06 /*Consumer IR*/ 224 225#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */ 226#define FCR_TXFTH1 0x20 /* for interrupt trigger */ 227 228/* 229 * Default NS87308 configuration 230 */ |
| 231#ifndef CFG_NS87308_KBC1_BASE 232#define CFG_NS87308_KBC1_BASE 0x0060 | 231#ifndef CONFIG_SYS_NS87308_KBC1_BASE 232#define CONFIG_SYS_NS87308_KBC1_BASE 0x0060 |
| 233#endif | 233#endif |
| 234#ifndef CFG_NS87308_RTC_BASE 235#define CFG_NS87308_RTC_BASE 0x0070 | 234#ifndef CONFIG_SYS_NS87308_RTC_BASE 235#define CONFIG_SYS_NS87308_RTC_BASE 0x0070 |
| 236#endif | 236#endif |
| 237#ifndef CFG_NS87308_FDC_BASE 238#define CFG_NS87308_FDC_BASE 0x03F0 | 237#ifndef CONFIG_SYS_NS87308_FDC_BASE 238#define CONFIG_SYS_NS87308_FDC_BASE 0x03F0 |
| 239#endif | 239#endif |
| 240#ifndef CFG_NS87308_LPT_BASE 241#define CFG_NS87308_LPT_BASE 0x0278 | 240#ifndef CONFIG_SYS_NS87308_LPT_BASE 241#define CONFIG_SYS_NS87308_LPT_BASE 0x0278 |
| 242#endif | 242#endif |
| 243#ifndef CFG_NS87308_UART1_BASE 244#define CFG_NS87308_UART1_BASE 0x03F8 | 243#ifndef CONFIG_SYS_NS87308_UART1_BASE 244#define CONFIG_SYS_NS87308_UART1_BASE 0x03F8 |
| 245#endif | 245#endif |
| 246#ifndef CFG_NS87308_UART2_BASE 247#define CFG_NS87308_UART2_BASE 0x02F8 | 246#ifndef CONFIG_SYS_NS87308_UART2_BASE 247#define CONFIG_SYS_NS87308_UART2_BASE 0x02F8 |
| 248#endif 249 250#endif /*_NS87308_H_*/ | 248#endif 249 250#endif /*_NS87308_H_*/ |