nand.h (794a5924972fc8073616e98a2668da4a5f9aea90) nand.h (cfa460adfdefcc30d104e1a9ee44994ee349bb7b)
1/*
2 * linux/include/linux/mtd/nand.h
3 *
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
1/*
2 * linux/include/linux/mtd/nand.h
3 *
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
8 * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Info:
15 * Contains standard defines and IDs for NAND flash devices
14 * Info:
15 * Contains standard defines and IDs for NAND flash devices
16 *
16 *
17 * Changelog:
18 * 01-31-2000 DMW Created
19 * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
20 * so it can be used by other NAND flash device
21 * drivers. I also changed the copyright since none
22 * of the original contents of this file are specific
23 * to DoC devices. David can whack me with a baseball
24 * bat later if I did something naughty.
25 * 10-11-2000 SJH Added private NAND flash structure for driver
26 * 10-24-2000 SJH Added prototype for 'nand_scan' function
27 * 10-29-2001 TG changed nand_chip structure to support
28 * hardwarespecific function for accessing control lines
29 * 02-21-2002 TG added support for different read/write adress and
30 * ready/busy line access function
31 * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
32 * command delay times for different chips
33 * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
34 * defines in jffs2/wbuf.c
35 * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
36 * CONFIG_MTD_NAND_ECC_JFFS2 is not set
37 * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
38 *
39 * 08-29-2002 tglx nand_chip structure: data_poi for selecting
40 * internal / fs-driver buffer
41 * support for 6byte/512byte hardware ECC
42 * read_ecc, write_ecc extended for different oob-layout
43 * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
44 * NAND_YAFFS_OOB
45 * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
46 * Split manufacturer and device ID structures
47 *
48 * 02-08-2004 tglx added option field to nand structure for chip anomalities
49 * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
50 * update of nand_chip structure description
17 * Changelog:
18 * See git changelog.
51 */
52#ifndef __LINUX_MTD_NAND_H
53#define __LINUX_MTD_NAND_H
54
19 */
20#ifndef __LINUX_MTD_NAND_H
21#define __LINUX_MTD_NAND_H
22
55#include <linux/mtd/compat.h>
23/* XXX U-BOOT XXX */
24#if 0
25#include <linux/wait.h>
26#include <linux/spinlock.h>
56#include <linux/mtd/mtd.h>
27#include <linux/mtd/mtd.h>
28#endif
57
29
30#include "config.h"
31
32#include "linux/mtd/compat.h"
33#include "linux/mtd/mtd.h"
34
35
58struct mtd_info;
59/* Scan and identify a NAND device */
60extern int nand_scan (struct mtd_info *mtd, int max_chips);
36struct mtd_info;
37/* Scan and identify a NAND device */
38extern int nand_scan (struct mtd_info *mtd, int max_chips);
39/* Separate phases of nand_scan(), allowing board driver to intervene
40 * and override command or ECC setup according to flash type */
41extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
42extern int nand_scan_tail(struct mtd_info *mtd);
43
61/* Free resources held by the NAND device */
62extern void nand_release (struct mtd_info *mtd);
63
44/* Free resources held by the NAND device */
45extern void nand_release (struct mtd_info *mtd);
46
64/* Read raw data from the device without ECC */
65extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
47/* Internal helper for board drivers which need to override command function */
48extern void nand_wait_ready(struct mtd_info *mtd);
66
49
50/* The maximum number of NAND chips in an array */
51#ifndef NAND_MAX_CHIPS
52#define NAND_MAX_CHIPS 8
53#endif
67
68/* This constant declares the max. oobsize / page, which
69 * is supported now. If you add a chip with bigger oobsize/page
70 * adjust this accordingly.
71 */
54
55/* This constant declares the max. oobsize / page, which
56 * is supported now. If you add a chip with bigger oobsize/page
57 * adjust this accordingly.
58 */
72#define NAND_MAX_OOBSIZE 64
59#define NAND_MAX_OOBSIZE 128
60#define NAND_MAX_PAGESIZE 4096
73
74/*
75 * Constants for hardware specific CLE/ALE/NCE function
61
62/*
63 * Constants for hardware specific CLE/ALE/NCE function
76*/
64 *
65 * These are bits which can be or'ed to set/clear multiple
66 * bits in one go.
67 */
77/* Select the chip by setting nCE to low */
68/* Select the chip by setting nCE to low */
78#define NAND_CTL_SETNCE 1
79/* Deselect the chip by setting nCE to high */
80#define NAND_CTL_CLRNCE 2
69#define NAND_NCE 0x01
81/* Select the command latch by setting CLE to high */
70/* Select the command latch by setting CLE to high */
82#define NAND_CTL_SETCLE 3
83/* Deselect the command latch by setting CLE to low */
84#define NAND_CTL_CLRCLE 4
71#define NAND_CLE 0x02
85/* Select the address latch by setting ALE to high */
72/* Select the address latch by setting ALE to high */
86#define NAND_CTL_SETALE 5
87/* Deselect the address latch by setting ALE to low */
88#define NAND_CTL_CLRALE 6
89/* Set write protection by setting WP to high. Not used! */
90#define NAND_CTL_SETWP 7
91/* Clear write protection by setting WP to low. Not used! */
92#define NAND_CTL_CLRWP 8
73#define NAND_ALE 0x04
93
74
75#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
76#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
77#define NAND_CTRL_CHANGE 0x80
78
94/*
95 * Standard NAND flash commands
96 */
97#define NAND_CMD_READ0 0
98#define NAND_CMD_READ1 1
79/*
80 * Standard NAND flash commands
81 */
82#define NAND_CMD_READ0 0
83#define NAND_CMD_READ1 1
84#define NAND_CMD_RNDOUT 5
99#define NAND_CMD_PAGEPROG 0x10
100#define NAND_CMD_READOOB 0x50
101#define NAND_CMD_ERASE1 0x60
102#define NAND_CMD_STATUS 0x70
103#define NAND_CMD_STATUS_MULTI 0x71
104#define NAND_CMD_SEQIN 0x80
85#define NAND_CMD_PAGEPROG 0x10
86#define NAND_CMD_READOOB 0x50
87#define NAND_CMD_ERASE1 0x60
88#define NAND_CMD_STATUS 0x70
89#define NAND_CMD_STATUS_MULTI 0x71
90#define NAND_CMD_SEQIN 0x80
91#define NAND_CMD_RNDIN 0x85
105#define NAND_CMD_READID 0x90
106#define NAND_CMD_ERASE2 0xd0
107#define NAND_CMD_RESET 0xff
108
109/* Extended commands for large page devices */
110#define NAND_CMD_READSTART 0x30
92#define NAND_CMD_READID 0x90
93#define NAND_CMD_ERASE2 0xd0
94#define NAND_CMD_RESET 0xff
95
96/* Extended commands for large page devices */
97#define NAND_CMD_READSTART 0x30
98#define NAND_CMD_RNDOUTSTART 0xE0
111#define NAND_CMD_CACHEDPROG 0x15
112
99#define NAND_CMD_CACHEDPROG 0x15
100
101/* Extended commands for AG-AND device */
102/*
103 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
104 * there is no way to distinguish that from NAND_CMD_READ0
105 * until the remaining sequence of commands has been completed
106 * so add a high order bit and mask it off in the command.
107 */
108#define NAND_CMD_DEPLETE1 0x100
109#define NAND_CMD_DEPLETE2 0x38
110#define NAND_CMD_STATUS_MULTI 0x71
111#define NAND_CMD_STATUS_ERROR 0x72
112/* multi-bank error status (banks 0-3) */
113#define NAND_CMD_STATUS_ERROR0 0x73
114#define NAND_CMD_STATUS_ERROR1 0x74
115#define NAND_CMD_STATUS_ERROR2 0x75
116#define NAND_CMD_STATUS_ERROR3 0x76
117#define NAND_CMD_STATUS_RESET 0x7f
118#define NAND_CMD_STATUS_CLEAR 0xff
119
120#define NAND_CMD_NONE -1
121
113/* Status bits */
114#define NAND_STATUS_FAIL 0x01
115#define NAND_STATUS_FAIL_N1 0x02
116#define NAND_STATUS_TRUE_READY 0x20
117#define NAND_STATUS_READY 0x40
118#define NAND_STATUS_WP 0x80
119
120/*
121 * Constants for ECC_MODES
122 */
122/* Status bits */
123#define NAND_STATUS_FAIL 0x01
124#define NAND_STATUS_FAIL_N1 0x02
125#define NAND_STATUS_TRUE_READY 0x20
126#define NAND_STATUS_READY 0x40
127#define NAND_STATUS_WP 0x80
128
129/*
130 * Constants for ECC_MODES
131 */
132typedef enum {
133 NAND_ECC_NONE,
134 NAND_ECC_SOFT,
135 NAND_ECC_HW,
136 NAND_ECC_HW_SYNDROME,
137} nand_ecc_modes_t;
123
138
124/* No ECC. Usage is not recommended ! */
125#define NAND_ECC_NONE 0
126/* Software ECC 3 byte ECC per 256 Byte data */
127#define NAND_ECC_SOFT 1
128/* Hardware ECC 3 byte ECC per 256 Byte data */
129#define NAND_ECC_HW3_256 2
130/* Hardware ECC 3 byte ECC per 512 Byte data */
131#define NAND_ECC_HW3_512 3
132/* Hardware ECC 6 byte ECC per 512 Byte data */
133#define NAND_ECC_HW6_512 4
134/* Hardware ECC 8 byte ECC per 512 Byte data */
135#define NAND_ECC_HW8_512 6
136/* Hardware ECC 12 byte ECC per 2048 Byte data */
137#define NAND_ECC_HW12_2048 7
138
139/*
140 * Constants for Hardware ECC
139/*
140 * Constants for Hardware ECC
141*/
141 */
142/* Reset Hardware ECC for read */
143#define NAND_ECC_READ 0
144/* Reset Hardware ECC for write */
145#define NAND_ECC_WRITE 1
146/* Enable Hardware ECC before syndrom is read back from flash */
147#define NAND_ECC_READSYN 2
148
142/* Reset Hardware ECC for read */
143#define NAND_ECC_READ 0
144/* Reset Hardware ECC for write */
145#define NAND_ECC_WRITE 1
146/* Enable Hardware ECC before syndrom is read back from flash */
147#define NAND_ECC_READSYN 2
148
149/* Bit mask for flags passed to do_nand_read_ecc */
150#define NAND_GET_DEVICE 0x80
151
152
149/* Option constants for bizarre disfunctionality and real
150* features
151*/
152/* Chip can not auto increment pages */
153#define NAND_NO_AUTOINCR 0x00000001
154/* Buswitdh is 16 bit */
155#define NAND_BUSWIDTH_16 0x00000002
156/* Device supports partial programming without padding */
157#define NAND_NO_PADDING 0x00000004
158/* Chip has cache program function */
159#define NAND_CACHEPRG 0x00000008
160/* Chip has copy back function */
161#define NAND_COPYBACK 0x00000010
162/* AND Chip which has 4 banks and a confusing page / block
163 * assignment. See Renesas datasheet for further information */
164#define NAND_IS_AND 0x00000020
165/* Chip has a array of 4 pages which can be read without
166 * additional ready /busy waits */
167#define NAND_4PAGE_ARRAY 0x00000040
153/* Option constants for bizarre disfunctionality and real
154* features
155*/
156/* Chip can not auto increment pages */
157#define NAND_NO_AUTOINCR 0x00000001
158/* Buswitdh is 16 bit */
159#define NAND_BUSWIDTH_16 0x00000002
160/* Device supports partial programming without padding */
161#define NAND_NO_PADDING 0x00000004
162/* Chip has cache program function */
163#define NAND_CACHEPRG 0x00000008
164/* Chip has copy back function */
165#define NAND_COPYBACK 0x00000010
166/* AND Chip which has 4 banks and a confusing page / block
167 * assignment. See Renesas datasheet for further information */
168#define NAND_IS_AND 0x00000020
169/* Chip has a array of 4 pages which can be read without
170 * additional ready /busy waits */
171#define NAND_4PAGE_ARRAY 0x00000040
172/* Chip requires that BBT is periodically rewritten to prevent
173 * bits from adjacent blocks from 'leaking' in altering data.
174 * This happens with the Renesas AG-AND chips, possibly others. */
175#define BBT_AUTO_REFRESH 0x00000080
176/* Chip does not require ready check on read. True
177 * for all large page devices, as they do not support
178 * autoincrement.*/
179#define NAND_NO_READRDY 0x00000100
180/* Chip does not allow subpage writes */
181#define NAND_NO_SUBPAGE_WRITE 0x00000200
168
182
183
169/* Options valid for Samsung large page devices */
170#define NAND_SAMSUNG_LP_OPTIONS \
171 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
172
173/* Macros to identify the above */
174#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
175#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
176#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
177#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
178
179/* Mask to zero out the chip options, which come from the id table */
180#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
181
182/* Non chip related options */
183/* Use a flash based bad block table. This option is passed to the
184 * default bad block table function. */
185#define NAND_USE_FLASH_BBT 0x00010000
184/* Options valid for Samsung large page devices */
185#define NAND_SAMSUNG_LP_OPTIONS \
186 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
187
188/* Macros to identify the above */
189#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
190#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
191#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
192#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
193
194/* Mask to zero out the chip options, which come from the id table */
195#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
196
197/* Non chip related options */
198/* Use a flash based bad block table. This option is passed to the
199 * default bad block table function. */
200#define NAND_USE_FLASH_BBT 0x00010000
186/* The hw ecc generator provides a syndrome instead a ecc value on read
187 * This can only work if we have the ecc bytes directly behind the
188 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
189#define NAND_HWECC_SYNDROME 0x00020000
190
191
201/* This option skips the bbt scan during initialization. */
202#define NAND_SKIP_BBTSCAN 0x00020000
203/* This option is defined if the board driver allocates its own buffers
204 (e.g. because it needs them DMA-coherent */
205#define NAND_OWN_BUFFERS 0x00040000
192/* Options set by nand scan */
206/* Options set by nand scan */
193/* Nand scan has allocated oob_buf */
194#define NAND_OOBBUF_ALLOC 0x40000000
195/* Nand scan has allocated data_buf */
196#define NAND_DATABUF_ALLOC 0x80000000
207/* Nand scan has allocated controller struct */
208#define NAND_CONTROLLER_ALLOC 0x80000000
197
209
210/* Cell info constants */
211#define NAND_CI_CHIPNR_MSK 0x03
212#define NAND_CI_CELLTYPE_MSK 0x0C
198
199/*
200 * nand_state_t - chip states
201 * Enumeration for NAND flash chip state
202 */
203typedef enum {
204 FL_READY,
205 FL_READING,
206 FL_WRITING,
207 FL_ERASING,
208 FL_SYNCING,
209 FL_CACHEDPRG,
213
214/*
215 * nand_state_t - chip states
216 * Enumeration for NAND flash chip state
217 */
218typedef enum {
219 FL_READY,
220 FL_READING,
221 FL_WRITING,
222 FL_ERASING,
223 FL_SYNCING,
224 FL_CACHEDPRG,
225 FL_PM_SUSPENDED,
210} nand_state_t;
211
212/* Keep gcc happy */
213struct nand_chip;
214
226} nand_state_t;
227
228/* Keep gcc happy */
229struct nand_chip;
230
215#if 0
216/**
231/**
217 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
218 * @lock: protection lock
232 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
233 * @lock: protection lock
219 * @active: the mtd device which holds the controller currently
234 * @active: the mtd device which holds the controller currently
235 * @wq: wait queue to sleep on if a NAND operation is in progress
236 * used instead of the per chip wait queue when a hw controller is available
220 */
221struct nand_hw_control {
237 */
238struct nand_hw_control {
222 spinlock_t lock;
223 struct nand_chip *active;
224};
239#if 0
240 spinlock_t lock;
241 wait_queue_head_t wq;
225#endif
242#endif
243 struct nand_chip *active;
244};
226
227/**
245
246/**
247 * struct nand_ecc_ctrl - Control structure for ecc
248 * @mode: ecc mode
249 * @steps: number of ecc steps per page
250 * @size: data bytes per ecc step
251 * @bytes: ecc bytes per step
252 * @total: total number of ecc bytes per page
253 * @prepad: padding information for syndrome based ecc generators
254 * @postpad: padding information for syndrome based ecc generators
255 * @layout: ECC layout control struct pointer
256 * @hwctl: function to control hardware ecc generator. Must only
257 * be provided if an hardware ECC is available
258 * @calculate: function for ecc calculation or readback from ecc hardware
259 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
260 * @read_page_raw: function to read a raw page without ECC
261 * @write_page_raw: function to write a raw page without ECC
262 * @read_page: function to read a page according to the ecc generator requirements
263 * @write_page: function to write a page according to the ecc generator requirements
264 * @read_oob: function to read chip OOB data
265 * @write_oob: function to write chip OOB data
266 */
267struct nand_ecc_ctrl {
268 nand_ecc_modes_t mode;
269 int steps;
270 int size;
271 int bytes;
272 int total;
273 int prepad;
274 int postpad;
275 struct nand_ecclayout *layout;
276 void (*hwctl)(struct mtd_info *mtd, int mode);
277 int (*calculate)(struct mtd_info *mtd,
278 const uint8_t *dat,
279 uint8_t *ecc_code);
280 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
281 uint8_t *read_ecc,
282 uint8_t *calc_ecc);
283 int (*read_page_raw)(struct mtd_info *mtd,
284 struct nand_chip *chip,
285 uint8_t *buf);
286 void (*write_page_raw)(struct mtd_info *mtd,
287 struct nand_chip *chip,
288 const uint8_t *buf);
289 int (*read_page)(struct mtd_info *mtd,
290 struct nand_chip *chip,
291 uint8_t *buf);
292 void (*write_page)(struct mtd_info *mtd,
293 struct nand_chip *chip,
294 const uint8_t *buf);
295 int (*read_oob)(struct mtd_info *mtd,
296 struct nand_chip *chip,
297 int page,
298 int sndcmd);
299 int (*write_oob)(struct mtd_info *mtd,
300 struct nand_chip *chip,
301 int page);
302};
303
304/**
305 * struct nand_buffers - buffer structure for read/write
306 * @ecccalc: buffer for calculated ecc
307 * @ecccode: buffer for ecc read from flash
308 * @databuf: buffer for data - dynamically sized
309 *
310 * Do not change the order of buffers. databuf and oobrbuf must be in
311 * consecutive order.
312 */
313struct nand_buffers {
314 uint8_t ecccalc[NAND_MAX_OOBSIZE];
315 uint8_t ecccode[NAND_MAX_OOBSIZE];
316 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
317};
318
319/**
228 * struct nand_chip - NAND Private Flash Chip Data
229 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
230 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
231 * @read_byte: [REPLACEABLE] read one byte from the chip
320 * struct nand_chip - NAND Private Flash Chip Data
321 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
322 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
323 * @read_byte: [REPLACEABLE] read one byte from the chip
232 * @write_byte: [REPLACEABLE] write one byte to the chip
233 * @read_word: [REPLACEABLE] read one word from the chip
324 * @read_word: [REPLACEABLE] read one word from the chip
234 * @write_word: [REPLACEABLE] write one word to the chip
235 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
236 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
237 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
238 * @select_chip: [REPLACEABLE] select chip nr
239 * @block_bad: [REPLACEABLE] check, if the block is bad
240 * @block_markbad: [REPLACEABLE] mark the block bad
325 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
326 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
327 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
328 * @select_chip: [REPLACEABLE] select chip nr
329 * @block_bad: [REPLACEABLE] check, if the block is bad
330 * @block_markbad: [REPLACEABLE] mark the block bad
241 * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
331 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
332 * ALE/CLE/nCE. Also used to write command and address
242 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
243 * If set to NULL no access to ready/busy is available and the ready/busy information
244 * is read from the chip status register
245 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
246 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
333 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
334 * If set to NULL no access to ready/busy is available and the ready/busy information
335 * is read from the chip status register
336 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
337 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
247 * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
248 * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
249 * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
250 * be provided if a hardware ECC is available
338 * @ecc: [BOARDSPECIFIC] ecc control ctructure
339 * @buffers: buffer structure for read/write
340 * @hwcontrol: platform-specific hardware control structure
341 * @ops: oob operation operands
251 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
252 * @scan_bbt: [REPLACEABLE] function to scan bad block table
342 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
343 * @scan_bbt: [REPLACEABLE] function to scan bad block table
253 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
254 * @eccsize: [INTERN] databytes used per ecc-calculation
255 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
256 * @eccsteps: [INTERN] number of ecc calculation steps per page
257 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
344 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
258 * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
259 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
260 * @state: [INTERN] the current state of the NAND device
345 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
346 * @state: [INTERN] the current state of the NAND device
347 * @oob_poi: poison value buffer
261 * @page_shift: [INTERN] number of address bits in a page (column address bits)
262 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
263 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
264 * @chip_shift: [INTERN] number of address bits in one chip
348 * @page_shift: [INTERN] number of address bits in a page (column address bits)
349 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
350 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
351 * @chip_shift: [INTERN] number of address bits in one chip
265 * @data_buf: [INTERN] internal buffer for one page + oob
266 * @oob_buf: [INTERN] oob buffer for one eraseblock
352 * @datbuf: [INTERN] internal buffer for one page + oob
353 * @oobbuf: [INTERN] oob buffer for one eraseblock
267 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
268 * @data_poi: [INTERN] pointer to a data buffer
269 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
270 * special functionality. See the defines for further explanation
271 * @badblockpos: [INTERN] position of the bad block marker in the oob area
354 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
355 * @data_poi: [INTERN] pointer to a data buffer
356 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
357 * special functionality. See the defines for further explanation
358 * @badblockpos: [INTERN] position of the bad block marker in the oob area
359 * @cellinfo: [INTERN] MLC/multichip data from chip ident
272 * @numchips: [INTERN] number of physical chips
273 * @chipsize: [INTERN] the size of one chip for multichip arrays
274 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
275 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
360 * @numchips: [INTERN] number of physical chips
361 * @chipsize: [INTERN] the size of one chip for multichip arrays
362 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
363 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
276 * @autooob: [REPLACEABLE] the default (auto)placement scheme
364 * @subpagesize: [INTERN] holds the subpagesize
365 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
277 * @bbt: [INTERN] bad block table pointer
278 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
279 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
280 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
366 * @bbt: [INTERN] bad block table pointer
367 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
368 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
369 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
281 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
370 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
371 * which is shared among multiple independend devices
282 * @priv: [OPTIONAL] pointer to private chip date
372 * @priv: [OPTIONAL] pointer to private chip date
373 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
374 * (determine if errors are correctable)
375 * @write_page: [REPLACEABLE] High-level page write function
283 */
284
285struct nand_chip {
286 void __iomem *IO_ADDR_R;
287 void __iomem *IO_ADDR_W;
288
376 */
377
378struct nand_chip {
379 void __iomem *IO_ADDR_R;
380 void __iomem *IO_ADDR_W;
381
289 u_char (*read_byte)(struct mtd_info *mtd);
290 void (*write_byte)(struct mtd_info *mtd, u_char byte);
382 uint8_t (*read_byte)(struct mtd_info *mtd);
291 u16 (*read_word)(struct mtd_info *mtd);
383 u16 (*read_word)(struct mtd_info *mtd);
292 void (*write_word)(struct mtd_info *mtd, u16 word);
293
294 void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
295 void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
296 int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
384 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
385 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
386 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
297 void (*select_chip)(struct mtd_info *mtd, int chip);
298 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
299 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
387 void (*select_chip)(struct mtd_info *mtd, int chip);
388 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
389 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
300 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
390 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
391 unsigned int ctrl);
301 int (*dev_ready)(struct mtd_info *mtd);
302 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
392 int (*dev_ready)(struct mtd_info *mtd);
393 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
303 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
304 int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
305 int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
306 void (*enable_hwecc)(struct mtd_info *mtd, int mode);
394 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
307 void (*erase_cmd)(struct mtd_info *mtd, int page);
308 int (*scan_bbt)(struct mtd_info *mtd);
395 void (*erase_cmd)(struct mtd_info *mtd, int page);
396 int (*scan_bbt)(struct mtd_info *mtd);
309 int eccmode;
310 int eccsize;
311 int eccbytes;
312 int eccsteps;
397 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
398 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
399 const uint8_t *buf, int page, int cached, int raw);
400
313 int chip_delay;
401 int chip_delay;
314#if 0
315 spinlock_t chip_lock;
316 wait_queue_head_t wq;
317 nand_state_t state;
318#endif
402 unsigned int options;
403
319 int page_shift;
320 int phys_erase_shift;
321 int bbt_erase_shift;
322 int chip_shift;
404 int page_shift;
405 int phys_erase_shift;
406 int bbt_erase_shift;
407 int chip_shift;
323 u_char *data_buf;
324 u_char *oob_buf;
325 int oobdirty;
326 u_char *data_poi;
327 unsigned int options;
328 int badblockpos;
329 int numchips;
330 unsigned long chipsize;
331 int pagemask;
332 int pagebuf;
408 int numchips;
409 unsigned long chipsize;
410 int pagemask;
411 int pagebuf;
333 struct nand_oobinfo *autooob;
412 int subpagesize;
413 uint8_t cellinfo;
414 int badblockpos;
415
416 nand_state_t state;
417
418 uint8_t *oob_poi;
419 struct nand_hw_control *controller;
420 struct nand_ecclayout *ecclayout;
421
422 struct nand_ecc_ctrl ecc;
423 struct nand_buffers *buffers;
424
425 struct nand_hw_control hwcontrol;
426
427 struct mtd_oob_ops ops;
428
334 uint8_t *bbt;
335 struct nand_bbt_descr *bbt_td;
336 struct nand_bbt_descr *bbt_md;
429 uint8_t *bbt;
430 struct nand_bbt_descr *bbt_td;
431 struct nand_bbt_descr *bbt_md;
432
337 struct nand_bbt_descr *badblock_pattern;
433 struct nand_bbt_descr *badblock_pattern;
338 struct nand_hw_control *controller;
434
339 void *priv;
340};
341
342/*
343 * NAND Flash Manufacturer ID Codes
344 */
345#define NAND_MFR_TOSHIBA 0x98
346#define NAND_MFR_SAMSUNG 0xec
347#define NAND_MFR_FUJITSU 0x04
348#define NAND_MFR_NATIONAL 0x8f
349#define NAND_MFR_RENESAS 0x07
350#define NAND_MFR_STMICRO 0x20
435 void *priv;
436};
437
438/*
439 * NAND Flash Manufacturer ID Codes
440 */
441#define NAND_MFR_TOSHIBA 0x98
442#define NAND_MFR_SAMSUNG 0xec
443#define NAND_MFR_FUJITSU 0x04
444#define NAND_MFR_NATIONAL 0x8f
445#define NAND_MFR_RENESAS 0x07
446#define NAND_MFR_STMICRO 0x20
447#define NAND_MFR_HYNIX 0xad
351#define NAND_MFR_MICRON 0x2c
352
353/**
354 * struct nand_flash_dev - NAND Flash Device ID Structure
448#define NAND_MFR_MICRON 0x2c
449
450/**
451 * struct nand_flash_dev - NAND Flash Device ID Structure
355 *
356 * @name: Identify the device type
357 * @id: device ID code
358 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
359 * If the pagesize is 0, then the real pagesize
360 * and the eraseize are determined from the
361 * extended id bytes in the chip
362 * @erasesize: Size of an erase block in the flash device.
363 * @chipsize: Total chipsize in Mega Bytes

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398 * @offs: offset of the pattern in the oob area of the page
399 * @veroffs: offset of the bbt version counter in the oob are of the page
400 * @version: version read from the bbt page during scan
401 * @len: length of the pattern, if 0 no pattern check is performed
402 * @maxblocks: maximum number of blocks to search for a bbt. This number of
403 * blocks is reserved at the end of the device where the tables are
404 * written.
405 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
452 * @name: Identify the device type
453 * @id: device ID code
454 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
455 * If the pagesize is 0, then the real pagesize
456 * and the eraseize are determined from the
457 * extended id bytes in the chip
458 * @erasesize: Size of an erase block in the flash device.
459 * @chipsize: Total chipsize in Mega Bytes

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494 * @offs: offset of the pattern in the oob area of the page
495 * @veroffs: offset of the bbt version counter in the oob are of the page
496 * @version: version read from the bbt page during scan
497 * @len: length of the pattern, if 0 no pattern check is performed
498 * @maxblocks: maximum number of blocks to search for a bbt. This number of
499 * blocks is reserved at the end of the device where the tables are
500 * written.
501 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
406 * bad) block in the stored bbt
502 * bad) block in the stored bbt
407 * @pattern: pattern to identify bad block table or factory marked good /
408 * bad blocks, can be NULL, if len = 0
409 *
410 * Descriptor for the bad block table marker and the descriptor for the
411 * pattern which identifies good and bad blocks. The assumption is made
412 * that the pattern and the version count are always located in the oob area
413 * of the first block.
414 */
415struct nand_bbt_descr {
416 int options;
417 int pages[NAND_MAX_CHIPS];
418 int offs;
419 int veroffs;
503 * @pattern: pattern to identify bad block table or factory marked good /
504 * bad blocks, can be NULL, if len = 0
505 *
506 * Descriptor for the bad block table marker and the descriptor for the
507 * pattern which identifies good and bad blocks. The assumption is made
508 * that the pattern and the version count are always located in the oob area
509 * of the first block.
510 */
511struct nand_bbt_descr {
512 int options;
513 int pages[NAND_MAX_CHIPS];
514 int offs;
515 int veroffs;
420 uint8_t version[NAND_MAX_CHIPS];
516 uint8_t version[NAND_MAX_CHIPS];
421 int len;
422 int maxblocks;
423 int reserved_block_code;
517 int len;
518 int maxblocks;
519 int reserved_block_code;
424 uint8_t *pattern;
520 uint8_t *pattern;
425};
426
427/* Options for the bad block table descriptors */
428
429/* The number of bits used per block in the bbt on the device */
430#define NAND_BBT_NRBITS_MSK 0x0000000F
431#define NAND_BBT_1BIT 0x00000001
432#define NAND_BBT_2BIT 0x00000002
433#define NAND_BBT_4BIT 0x00000004
434#define NAND_BBT_8BIT 0x00000008
435/* The bad block table is in the last good block of the device */
521};
522
523/* Options for the bad block table descriptors */
524
525/* The number of bits used per block in the bbt on the device */
526#define NAND_BBT_NRBITS_MSK 0x0000000F
527#define NAND_BBT_1BIT 0x00000001
528#define NAND_BBT_2BIT 0x00000002
529#define NAND_BBT_4BIT 0x00000004
530#define NAND_BBT_8BIT 0x00000008
531/* The bad block table is in the last good block of the device */
436#define NAND_BBT_LASTBLOCK 0x00000010
532#define NAND_BBT_LASTBLOCK 0x00000010
437/* The bbt is at the given page, else we must scan for the bbt */
438#define NAND_BBT_ABSPAGE 0x00000020
439/* The bbt is at the given page, else we must scan for the bbt */
440#define NAND_BBT_SEARCH 0x00000040
441/* bbt is stored per chip on multichip devices */
442#define NAND_BBT_PERCHIP 0x00000080
443/* bbt has a version counter at offset veroffs */
444#define NAND_BBT_VERSION 0x00000100

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451/* Write bbt if neccecary */
452#define NAND_BBT_WRITE 0x00001000
453/* Read and write back block contents when writing bbt */
454#define NAND_BBT_SAVECONTENT 0x00002000
455/* Search good / bad pattern on the first and the second page */
456#define NAND_BBT_SCAN2NDPAGE 0x00004000
457
458/* The maximum number of blocks to scan for a bbt */
533/* The bbt is at the given page, else we must scan for the bbt */
534#define NAND_BBT_ABSPAGE 0x00000020
535/* The bbt is at the given page, else we must scan for the bbt */
536#define NAND_BBT_SEARCH 0x00000040
537/* bbt is stored per chip on multichip devices */
538#define NAND_BBT_PERCHIP 0x00000080
539/* bbt has a version counter at offset veroffs */
540#define NAND_BBT_VERSION 0x00000100

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547/* Write bbt if neccecary */
548#define NAND_BBT_WRITE 0x00001000
549/* Read and write back block contents when writing bbt */
550#define NAND_BBT_SAVECONTENT 0x00002000
551/* Search good / bad pattern on the first and the second page */
552#define NAND_BBT_SCAN2NDPAGE 0x00004000
553
554/* The maximum number of blocks to scan for a bbt */
459#define NAND_BBT_SCAN_MAXBLOCKS 4
555#define NAND_BBT_SCAN_MAXBLOCKS 4
460
556
461extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
462extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
463extern int nand_default_bbt (struct mtd_info *mtd);
464extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
465extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
557extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
558extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
559extern int nand_default_bbt(struct mtd_info *mtd);
560extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
561extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
562 int allowbbt);
563extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
564 size_t * retlen, uint8_t * buf);
466
467/*
468* Constants for oob configuration
469*/
470#define NAND_SMALL_BADBLOCK_POS 5
471#define NAND_LARGE_BADBLOCK_POS 0
472
565
566/*
567* Constants for oob configuration
568*/
569#define NAND_SMALL_BADBLOCK_POS 5
570#define NAND_LARGE_BADBLOCK_POS 0
571
572/**
573 * struct platform_nand_chip - chip level device structure
574 * @nr_chips: max. number of chips to scan for
575 * @chip_offset: chip number offset
576 * @nr_partitions: number of partitions pointed to by partitions (or zero)
577 * @partitions: mtd partition list
578 * @chip_delay: R/B delay value in us
579 * @options: Option flags, e.g. 16bit buswidth
580 * @ecclayout: ecc layout info structure
581 * @part_probe_types: NULL-terminated array of probe types
582 * @priv: hardware controller specific settings
583 */
584struct platform_nand_chip {
585 int nr_chips;
586 int chip_offset;
587 int nr_partitions;
588 struct mtd_partition *partitions;
589 struct nand_ecclayout *ecclayout;
590 int chip_delay;
591 unsigned int options;
592 const char **part_probe_types;
593 void *priv;
594};
595
596/**
597 * struct platform_nand_ctrl - controller level device structure
598 * @hwcontrol: platform specific hardware control structure
599 * @dev_ready: platform specific function to read ready/busy pin
600 * @select_chip: platform specific chip select function
601 * @cmd_ctrl: platform specific function for controlling
602 * ALE/CLE/nCE. Also used to write command and address
603 * @priv: private data to transport driver specific settings
604 *
605 * All fields are optional and depend on the hardware driver requirements
606 */
607struct platform_nand_ctrl {
608 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
609 int (*dev_ready)(struct mtd_info *mtd);
610 void (*select_chip)(struct mtd_info *mtd, int chip);
611 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
612 unsigned int ctrl);
613 void *priv;
614};
615
616/**
617 * struct platform_nand_data - container structure for platform-specific data
618 * @chip: chip level chip structure
619 * @ctrl: controller level device structure
620 */
621struct platform_nand_data {
622 struct platform_nand_chip chip;
623 struct platform_nand_ctrl ctrl;
624};
625
626/* Some helpers to access the data structures */
627static inline
628struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
629{
630 struct nand_chip *chip = mtd->priv;
631
632 return chip->priv;
633}
634
473#endif /* __LINUX_MTD_NAND_H */
635#endif /* __LINUX_MTD_NAND_H */