sh7757lcr.h (e89f8aae3d67cd3d2d04cedd9735c5e5fd32b621) sh7757lcr.h (1ddbcf46bfba605b65f111a9f1f6c50098957767)
1/*
2 * Configuation settings for the sh7757lcr board
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8

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59
60/* Gigabit Ether */
61#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
62
63/* SPI */
64#define CONFIG_SH_SPI_BASE 0xfe002000
65
66/* MMCIF */
1/*
2 * Configuation settings for the sh7757lcr board
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8

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59
60/* Gigabit Ether */
61#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
62
63/* SPI */
64#define CONFIG_SH_SPI_BASE 0xfe002000
65
66/* MMCIF */
67#define CONFIG_SH_MMCIF 1
68#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
69#define CONFIG_SH_MMCIF_CLK 48000000
70
71/* SH7757 board */
72#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
73#define SH7757LCR_GRA_OFFSET 0x1f000000
74#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
75#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)

--- 20 unchanged lines hidden --- 		67#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
68#define CONFIG_SH_MMCIF_CLK 48000000
69
70/* SH7757 board */
71#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
72#define SH7757LCR_GRA_OFFSET 0x1f000000
73#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
74#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)

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