| mpr2.h (becbbc7b2a1be44d38779c80ce94fb20e5e13f12) | mpr2.h (5a1aceb0689e2f731491838970884a673ef7e7d3) |
|---|---|
| 1/* 2 * Configuation settings for MPR2 3 * 4 * Copyright (C) 2008 5 * Mark Jonas <mark.jonas@de.bosch.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. --- 59 unchanged lines hidden (view full) --- 68/* Flash */ 69#define CFG_FLASH_CFI 70#define CONFIG_FLASH_CFI_DRIVER 71#define CFG_FLASH_EMPTY_INFO 72#define CFG_FLASH_BASE 0xA0000000 73#define CFG_MAX_FLASH_SECT 256 74#define CFG_MAX_FLASH_BANKS 1 75#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | 1/* 2 * Configuation settings for MPR2 3 * 4 * Copyright (C) 2008 5 * Mark Jonas <mark.jonas@de.bosch.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. --- 59 unchanged lines hidden (view full) --- 68/* Flash */ 69#define CFG_FLASH_CFI 70#define CONFIG_FLASH_CFI_DRIVER 71#define CFG_FLASH_EMPTY_INFO 72#define CFG_FLASH_BASE 0xA0000000 73#define CFG_MAX_FLASH_SECT 256 74#define CFG_MAX_FLASH_BANKS 1 75#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
| 76#define CFG_ENV_IS_IN_FLASH | 76#define CONFIG_ENV_IS_IN_FLASH |
| 77#define CFG_ENV_SECT_SIZE (128 * 1024) 78#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE 79#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 80#define CFG_FLASH_ERASE_TOUT 120000 81#define CFG_FLASH_WRITE_TOUT 500 82 83/* Clocks */ 84#define CONFIG_SYS_CLK_FREQ 24000000 85#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ 86#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) 87 88/* UART */ 89#define CONFIG_SCIF_CONSOLE 1 90#define CONFIG_CONS_SCIF0 1 91 92#endif /* __MPR2_H */ | 77#define CFG_ENV_SECT_SIZE (128 * 1024) 78#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE 79#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 80#define CFG_FLASH_ERASE_TOUT 120000 81#define CFG_FLASH_WRITE_TOUT 500 82 83/* Clocks */ 84#define CONFIG_SYS_CLK_FREQ 24000000 85#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ 86#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) 87 88/* UART */ 89#define CONFIG_SCIF_CONSOLE 1 90#define CONFIG_CONS_SCIF0 1 91 92#endif /* __MPR2_H */ |