at91sam9263ek.h (92afd368bba7d98b2b7bfb51082c3639bb2119b3) at91sam9263ek.h (1b3b7c640d04df2ba9a9d947117d112a75fee7f4)
1/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9263EK board.
7 *
8 * See file CREDITS for list of people who contributed to this

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36#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
37#define CONFIG_ARCH_CPU_INIT
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39
40#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS 1
42#define CONFIG_INITRD_TAG 1
43
1/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9263EK board.
7 *
8 * See file CREDITS for list of people who contributed to this

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36#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
37#define CONFIG_ARCH_CPU_INIT
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39
40#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS 1
42#define CONFIG_INITRD_TAG 1
43
44#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
44#define CONFIG_SKIP_LOWLEVEL_INIT
45#define CONFIG_SKIP_RELOCATE_UBOOT
45#define CONFIG_SKIP_LOWLEVEL_INIT
46#define CONFIG_SKIP_RELOCATE_UBOOT
47#endif
46
47/*
48 * Hardware drivers
49 */
50#define CONFIG_ATMEL_USART 1
51#undef CONFIG_USART0
52#undef CONFIG_USART1
53#undef CONFIG_USART2

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108#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
109#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
110#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
111#define AT91_SPI_CLK 15000000
112#define DATAFLASH_TCSS (0x1a << 16)
113#define DATAFLASH_TCHS (0x1 << 24)
114
115/* NOR flash, if populated */
48
49/*
50 * Hardware drivers
51 */
52#define CONFIG_ATMEL_USART 1
53#undef CONFIG_USART0
54#undef CONFIG_USART1
55#undef CONFIG_USART2

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110#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
111#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
112#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
113#define AT91_SPI_CLK 15000000
114#define DATAFLASH_TCSS (0x1a << 16)
115#define DATAFLASH_TCHS (0x1 << 24)
116
117/* NOR flash, if populated */
116#if 1
117#define CONFIG_SYS_NO_FLASH 1
118#else
118#ifdef CONFIG_SYS_USE_NORFLASH
119#define CONFIG_SYS_FLASH_CFI 1
119#define CONFIG_SYS_FLASH_CFI 1
120#define CONFIG_FLASH_CFI_DRIVER 1
121#define PHYS_FLASH_1 0x10000000
120#define CONFIG_FLASH_CFI_DRIVER 1
121#define PHYS_FLASH_1 0x10000000
122#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
123#define CONFIG_SYS_MAX_FLASH_SECT 256
124#define CONFIG_SYS_MAX_FLASH_BANKS 1
122#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
123#define CONFIG_SYS_MAX_FLASH_SECT 256
124#define CONFIG_SYS_MAX_FLASH_BANKS 1
125
126#define CONFIG_SYS_MONITOR_SEC 1:0-3
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
128#define CONFIG_SYS_MONITOR_LEN (256 << 10)
129#define CONFIG_ENV_IS_IN_FLASH 1
130#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
131#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
132
133/* Address and size of Primary Environment Sector */
134#define CONFIG_ENV_SIZE 0x2000
135
136#define xstr(s) str(s)
137#define str(s) #s
138
139#define CONFIG_EXTRA_ENV_SETTINGS \
140 "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
141 "update=" \
142 "protect off ${monitor_base} +${filesize};" \
143 "erase ${monitor_base} +${filesize};" \
144 "cp.b ${load_addr} ${monitor_base} ${filesize};" \
145 "protect on ${monitor_base} +${filesize}\0"
146
147#ifndef CONFIG_SKIP_LOWLEVEL_INIT
148#define MASTER_PLL_MUL 171
149#define MASTER_PLL_DIV 14
150
151/* clocks */
152#define CONFIG_SYS_MOR_VAL \
153 (AT91_PMC_MOSCEN | \
154 (255 << 8)) /* Main Oscillator Start-up Time */
155#define CONFIG_SYS_PLLAR_VAL \
156 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
157 AT91_PMC_OUT | \
158 AT91_PMC_PLLCOUNT | /* PLL Counter */ \
159 (2 << 28) | /* PLL Clock Frequency Range */ \
160 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
161
162/* PCK/2 = MCK Master Clock from PLLA */
163#define CONFIG_SYS_MCKR1_VAL \
164 (AT91_PMC_CSS_SLOW | \
165 AT91_PMC_PRES_1 | \
166 AT91SAM9_PMC_MDIV_2 | \
167 AT91_PMC_PDIV_1)
168/* PCK/2 = MCK Master Clock from PLLA */
169#define CONFIG_SYS_MCKR2_VAL \
170 (AT91_PMC_CSS_PLLA | \
171 AT91_PMC_PRES_1 | \
172 AT91SAM9_PMC_MDIV_2 | \
173 AT91_PMC_PDIV_1)
174
175/* define PDC[31:16] as DATA[31:16] */
176#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
177/* no pull-up for D[31:16] */
178#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
179/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
180#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
181 (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
182 AT91_MATRIX_EBI0_CS1A_SDRAMC)
183
184/* SDRAM */
185/* SDRAMC_MR Mode register */
186#define CONFIG_SYS_SDRC_MR_VAL1 0
187/* SDRAMC_TR - Refresh Timer register */
188#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
189/* SDRAMC_CR - Configuration register*/
190#define CONFIG_SYS_SDRC_CR_VAL \
191 (AT91_SDRAMC_NC_9 | \
192 AT91_SDRAMC_NR_13 | \
193 AT91_SDRAMC_NB_4 | \
194 AT91_SDRAMC_CAS_3 | \
195 AT91_SDRAMC_DBW_32 | \
196 (1 << 8) | /* Write Recovery Delay */ \
197 (7 << 12) | /* Row Cycle Delay */ \
198 (2 << 16) | /* Row Precharge Delay */ \
199 (2 << 20) | /* Row to Column Delay */ \
200 (5 << 24) | /* Active to Precharge Delay */ \
201 (1 << 28)) /* Exit Self Refresh to Active Delay */
202
203/* Memory Device Register -> SDRAM */
204#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
205#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
206#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
207#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
208#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
209#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
210#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
211#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
212#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
213#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
214#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
215#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
216#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
217#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
218#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
219#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
220#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
221#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
222
223/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
224#define CONFIG_SYS_SMC0_SETUP0_VAL \
225 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
226 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
227#define CONFIG_SYS_SMC0_PULSE0_VAL \
228 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
229 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
230#define CONFIG_SYS_SMC0_CYCLE0_VAL \
231 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
232#define CONFIG_SYS_SMC0_MODE0_VAL \
233 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
234 AT91_SMC_DBW_16 | \
235 AT91_SMC_TDFMODE | \
236 AT91_SMC_TDF_(6))
237
238/* user reset enable */
239#define CONFIG_SYS_RSTC_RMR_VAL \
240 (AT91_RSTC_KEY | \
241 AT91_RSTC_PROCRST | \
242 AT91_RSTC_RSTTYP_WAKEUP | \
243 AT91_RSTC_RSTTYP_WATCHDOG)
244
245/* Disable Watchdog */
246#define CONFIG_SYS_WDTC_WDMR_VAL \
247 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
248 AT91_WDT_WDV | \
249 AT91_WDT_WDDIS | \
250 AT91_WDT_WDD)
125#endif
126
251#endif
252
253#else
254#define CONFIG_SYS_NO_FLASH 1
255#endif
256
127/* NAND flash */
128#ifdef CONFIG_CMD_NAND
129#define CONFIG_NAND_ATMEL
130#define CONFIG_SYS_MAX_NAND_DEVICE 1
131#define CONFIG_SYS_NAND_BASE 0x40000000
132#define CONFIG_SYS_NAND_DBW_8 1
133/* our ALE is AD21 */
134#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

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170#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
171#define CONFIG_ENV_SIZE 0x4200
172#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
173#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
174 "root=/dev/mtdblock0 " \
175 "mtdparts=at91_nand:-(root) "\
176 "rw rootfstype=jffs2"
177
257/* NAND flash */
258#ifdef CONFIG_CMD_NAND
259#define CONFIG_NAND_ATMEL
260#define CONFIG_SYS_MAX_NAND_DEVICE 1
261#define CONFIG_SYS_NAND_BASE 0x40000000
262#define CONFIG_SYS_NAND_DBW_8 1
263/* our ALE is AD21 */
264#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)

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300#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
301#define CONFIG_ENV_SIZE 0x4200
302#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
303#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
304 "root=/dev/mtdblock0 " \
305 "mtdparts=at91_nand:-(root) "\
306 "rw rootfstype=jffs2"
307
178#else /* CONFIG_SYS_USE_NANDFLASH */
308#elif CONFIG_SYS_USE_NANDFLASH
179
180/* bootstrap + u-boot + env + linux in nandflash */
181#define CONFIG_ENV_IS_IN_NAND 1
182#define CONFIG_ENV_OFFSET 0x60000
183#define CONFIG_ENV_OFFSET_REDUND 0x80000
184#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
185#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
186#define CONFIG_BOOTARGS "console=ttyS0,115200 " \

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310/* bootstrap + u-boot + env + linux in nandflash */
311#define CONFIG_ENV_IS_IN_NAND 1
312#define CONFIG_ENV_OFFSET 0x60000
313#define CONFIG_ENV_OFFSET_REDUND 0x80000
314#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
315#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
316#define CONFIG_BOOTARGS "console=ttyS0,115200 " \

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