vsc7385.c (794a5924972fc8073616e98a2668da4a5f9aea90) vsc7385.c (6d0f6bcf337c5261c08fabe12982178c2c489d76)
1/*
2 * Vitesse 7385 Switch Firmware Upload
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
7 * under the terms of the GNU General Public License version 2. This
8 * program is licensed "as is" without any warranty of any kind, whether

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30 *
31 * Further details on the register information can be obtained from Vitesse.
32 */
33int vsc7385_upload_firmware(void *firmware, unsigned int size)
34{
35 u8 *fw = firmware;
36 unsigned int i;
37
1/*
2 * Vitesse 7385 Switch Firmware Upload
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
7 * under the terms of the GNU General Public License version 2. This
8 * program is licensed "as is" without any warranty of any kind, whether

--- 21 unchanged lines hidden (view full) ---

30 *
31 * Further details on the register information can be obtained from Vitesse.
32 */
33int vsc7385_upload_firmware(void *firmware, unsigned int size)
34{
35 u8 *fw = firmware;
36 unsigned int i;
37
38 u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
39 u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
40 u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
41 u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
42 u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
38 u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
39 u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
40 u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
41 u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
42 u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
43#ifdef DEBUG
43#ifdef DEBUG
44 u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
44 u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
45#endif
46
47 out_be32(gloreset, 3);
48 udelay(200);
49
50 out_be32(icpu_ctrl, 0x8E);
51 udelay(20);
52

--- 44 unchanged lines hidden --- 		45#endif
46
47 out_be32(gloreset, 3);
48 udelay(200);
49
50 out_be32(icpu_ctrl, 0x8E);
51 udelay(20);
52

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