tsec.c (56a27a1e6cbc414a8d5b9e59314119777c092635) tsec.c (9a1d6af55ecd73938d49076422e87da9f87fc68f)
1/*
2 * Freescale Three Speed Ethernet Controller driver
3 *
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
6 * author Andy Fleming
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <config.h>
12#include <common.h>
1/*
2 * Freescale Three Speed Ethernet Controller driver
3 *
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
6 * author Andy Fleming
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <config.h>
12#include <common.h>
13#include <dm.h>
13#include <malloc.h>
14#include <net.h>
15#include <command.h>
16#include <tsec.h>
17#include <fsl_mdio.h>
18#include <asm/errno.h>
19#include <asm/processor.h>
20#include <asm/io.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
14#include <malloc.h>
15#include <net.h>
16#include <command.h>
17#include <tsec.h>
18#include <fsl_mdio.h>
19#include <asm/errno.h>
20#include <asm/processor.h>
21#include <asm/io.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#ifndef CONFIG_DM_ETH
24/* Default initializations for TSEC controllers. */
25
26static struct tsec_info_struct tsec_info[] = {
27#ifdef CONFIG_TSEC1
28 STD_TSEC_INFO(1), /* TSEC1 */
29#endif
30#ifdef CONFIG_TSEC2
31 STD_TSEC_INFO(2), /* TSEC2 */

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41#endif
42#ifdef CONFIG_TSEC3
43 STD_TSEC_INFO(3), /* TSEC3 */
44#endif
45#ifdef CONFIG_TSEC4
46 STD_TSEC_INFO(4), /* TSEC4 */
47#endif
48};
26/* Default initializations for TSEC controllers. */
27
28static struct tsec_info_struct tsec_info[] = {
29#ifdef CONFIG_TSEC1
30 STD_TSEC_INFO(1), /* TSEC1 */
31#endif
32#ifdef CONFIG_TSEC2
33 STD_TSEC_INFO(2), /* TSEC2 */

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43#endif
44#ifdef CONFIG_TSEC3
45 STD_TSEC_INFO(3), /* TSEC3 */
46#endif
47#ifdef CONFIG_TSEC4
48 STD_TSEC_INFO(4), /* TSEC4 */
49#endif
50};
51#endif /* CONFIG_DM_ETH */
49
50#define TBIANA_SETTINGS ( \
51 TBIANA_ASYMMETRIC_PAUSE \
52 | TBIANA_SYMMETRIC_PAUSE \
53 | TBIANA_FULL_DUPLEX \
54 )
55
56/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */

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93 * table. The table is controlled through 8 32-bit registers:
94 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
95 * 255. This means that the 3 most significant bits in the
96 * hash index which gaddr register to use, and the 5 other bits
97 * indicate which bit (assuming an IBM numbering scheme, which
98 * for PowerPC (tm) is usually the case) in the register holds
99 * the entry.
100 */
52
53#define TBIANA_SETTINGS ( \
54 TBIANA_ASYMMETRIC_PAUSE \
55 | TBIANA_SYMMETRIC_PAUSE \
56 | TBIANA_FULL_DUPLEX \
57 )
58
59/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */

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96 * table. The table is controlled through 8 32-bit registers:
97 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
98 * 255. This means that the 3 most significant bits in the
99 * hash index which gaddr register to use, and the 5 other bits
100 * indicate which bit (assuming an IBM numbering scheme, which
101 * for PowerPC (tm) is usually the case) in the register holds
102 * the entry.
103 */
104#ifndef CONFIG_DM_ETH
101static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
105static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
106#else
107static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
108#endif
102{
103 struct tsec_private *priv = (struct tsec_private *)dev->priv;
104 struct tsec __iomem *regs = priv->regs;
105 u32 result, value;
106 u8 whichbit, whichreg;
107
108 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
109 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */

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220}
221
222/*
223 * This returns the status bits of the device. The return value
224 * is never checked, and this is what the 8260 driver did, so we
225 * do the same. Presumably, this would be zero if there were no
226 * errors
227 */
109{
110 struct tsec_private *priv = (struct tsec_private *)dev->priv;
111 struct tsec __iomem *regs = priv->regs;
112 u32 result, value;
113 u8 whichbit, whichreg;
114
115 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
116 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */

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227}
228
229/*
230 * This returns the status bits of the device. The return value
231 * is never checked, and this is what the 8260 driver did, so we
232 * do the same. Presumably, this would be zero if there were no
233 * errors
234 */
235#ifndef CONFIG_DM_ETH
228static int tsec_send(struct eth_device *dev, void *packet, int length)
236static int tsec_send(struct eth_device *dev, void *packet, int length)
237#else
238static int tsec_send(struct udevice *dev, void *packet, int length)
239#endif
229{
230 struct tsec_private *priv = (struct tsec_private *)dev->priv;
231 struct tsec __iomem *regs = priv->regs;
232 uint16_t status;
233 int result = 0;
234 int i;
235
236 /* Find an empty buffer descriptor */

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263 }
264
265 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
266 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
267
268 return result;
269}
270
240{
241 struct tsec_private *priv = (struct tsec_private *)dev->priv;
242 struct tsec __iomem *regs = priv->regs;
243 uint16_t status;
244 int result = 0;
245 int i;
246
247 /* Find an empty buffer descriptor */

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274 }
275
276 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
277 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
278
279 return result;
280}
281
282#ifndef CONFIG_DM_ETH
271static int tsec_recv(struct eth_device *dev)
272{
273 struct tsec_private *priv = (struct tsec_private *)dev->priv;
274 struct tsec __iomem *regs = priv->regs;
275
276 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
277 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
278 uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);

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297
298 if (in_be32(&regs->ievent) & IEVENT_BSY) {
299 out_be32(&regs->ievent, IEVENT_BSY);
300 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
301 }
302
303 return -1;
304}
283static int tsec_recv(struct eth_device *dev)
284{
285 struct tsec_private *priv = (struct tsec_private *)dev->priv;
286 struct tsec __iomem *regs = priv->regs;
287
288 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
289 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
290 uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);

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309
310 if (in_be32(&regs->ievent) & IEVENT_BSY) {
311 out_be32(&regs->ievent, IEVENT_BSY);
312 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
313 }
314
315 return -1;
316}
317#else
318static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
319{
320 struct tsec_private *priv = (struct tsec_private *)dev->priv;
321 struct tsec __iomem *regs = priv->regs;
322 int ret = -1;
305
323
324 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
325 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
326 uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
327 uint32_t buf;
328
329 /* Send the packet up if there were no errors */
330 if (!(status & RXBD_STATS)) {
331 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
332 *packetp = (uchar *)buf;
333 ret = length - 4;
334 } else {
335 printf("Got error %x\n", (status & RXBD_STATS));
336 }
337 }
338
339 if (in_be32(&regs->ievent) & IEVENT_BSY) {
340 out_be32(&regs->ievent, IEVENT_BSY);
341 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
342 }
343
344 return ret;
345}
346
347static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
348{
349 struct tsec_private *priv = (struct tsec_private *)dev->priv;
350 uint16_t status;
351
352 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
353
354 status = RXBD_EMPTY;
355 /* Set the wrap bit if this is the last element in the list */
356 if ((priv->rx_idx + 1) == PKTBUFSRX)
357 status |= RXBD_WRAP;
358 out_be16(&priv->rxbd[priv->rx_idx].status, status);
359
360 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
361
362 return 0;
363}
364#endif
365
306/* Stop the interface */
366/* Stop the interface */
367#ifndef CONFIG_DM_ETH
307static void tsec_halt(struct eth_device *dev)
368static void tsec_halt(struct eth_device *dev)
369#else
370static void tsec_halt(struct udevice *dev)
371#endif
308{
309 struct tsec_private *priv = (struct tsec_private *)dev->priv;
310 struct tsec __iomem *regs = priv->regs;
311
312 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
313 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
314
315 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))

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462}
463
464/*
465 * Initializes data structures and registers for the controller,
466 * and brings the interface up. Returns the link status, meaning
467 * that it returns success if the link is up, failure otherwise.
468 * This allows U-Boot to find the first active controller.
469 */
372{
373 struct tsec_private *priv = (struct tsec_private *)dev->priv;
374 struct tsec __iomem *regs = priv->regs;
375
376 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
377 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
378
379 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))

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526}
527
528/*
529 * Initializes data structures and registers for the controller,
530 * and brings the interface up. Returns the link status, meaning
531 * that it returns success if the link is up, failure otherwise.
532 * This allows U-Boot to find the first active controller.
533 */
534#ifndef CONFIG_DM_ETH
470static int tsec_init(struct eth_device *dev, bd_t * bd)
535static int tsec_init(struct eth_device *dev, bd_t * bd)
536#else
537static int tsec_init(struct udevice *dev)
538#endif
471{
472 struct tsec_private *priv = (struct tsec_private *)dev->priv;
539{
540 struct tsec_private *priv = (struct tsec_private *)dev->priv;
541#ifdef CONFIG_DM_ETH
542 struct eth_pdata *pdata = dev_get_platdata(dev);
543#endif
473 struct tsec __iomem *regs = priv->regs;
474 u32 tempval;
475 int ret;
476
477 /* Make sure the controller is stopped */
478 tsec_halt(dev);
479
480 /* Init MACCFG2. Defaults to GMII */
481 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
482
483 /* Init ECNTRL */
484 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
485
486 /*
487 * Copy the station address into the address registers.
488 * For a station address of 0x12345678ABCD in transmission
489 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
490 * MACnADDR2 is set to 0x34120000.
491 */
544 struct tsec __iomem *regs = priv->regs;
545 u32 tempval;
546 int ret;
547
548 /* Make sure the controller is stopped */
549 tsec_halt(dev);
550
551 /* Init MACCFG2. Defaults to GMII */
552 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
553
554 /* Init ECNTRL */
555 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
556
557 /*
558 * Copy the station address into the address registers.
559 * For a station address of 0x12345678ABCD in transmission
560 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
561 * MACnADDR2 is set to 0x34120000.
562 */
563#ifndef CONFIG_DM_ETH
492 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
493 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
564 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
565 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
566#else
567 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
568 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
569#endif
494
495 out_be32(&regs->macstnaddr1, tempval);
496
570
571 out_be32(&regs->macstnaddr1, tempval);
572
573#ifndef CONFIG_DM_ETH
497 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
574 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
575#else
576 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
577#endif
498
499 out_be32(&regs->macstnaddr2, tempval);
500
501 /* Clear out (for the most part) the other registers */
502 init_registers(regs);
503
504 /* Ready the device for tx/rx */
505 startup_tsec(priv);

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595
596 priv->phydev = phydev;
597
598 phy_config(phydev);
599
600 return 1;
601}
602
578
579 out_be32(&regs->macstnaddr2, tempval);
580
581 /* Clear out (for the most part) the other registers */
582 init_registers(regs);
583
584 /* Ready the device for tx/rx */
585 startup_tsec(priv);

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675
676 priv->phydev = phydev;
677
678 phy_config(phydev);
679
680 return 1;
681}
682
683#ifndef CONFIG_DM_ETH
603/*
604 * Initialize device structure. Returns success if PHY
605 * initialization succeeded (i.e. if it recognizes the PHY)
606 */
607static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
608{
609 struct eth_device *dev;
610 int i;

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682
683 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
684 info.name = DEFAULT_MII_NAME;
685
686 fsl_pq_mdio_init(bis, &info);
687
688 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
689}
684/*
685 * Initialize device structure. Returns success if PHY
686 * initialization succeeded (i.e. if it recognizes the PHY)
687 */
688static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
689{
690 struct eth_device *dev;
691 int i;

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763
764 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
765 info.name = DEFAULT_MII_NAME;
766
767 fsl_pq_mdio_init(bis, &info);
768
769 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
770}
771#else /* CONFIG_DM_ETH */
772int tsec_probe(struct udevice *dev)
773{
774 struct tsec_private *priv = dev_get_priv(dev);
775 struct eth_pdata *pdata = dev_get_platdata(dev);
776 struct fsl_pq_mdio_info mdio_info;
777 int offset = 0;
778 int reg;
779 const char *phy_mode;
780 int ret;
781
782 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
783 priv->regs = (struct tsec *)pdata->iobase;
784
785 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
786 "phy-handle");
787 if (offset > 0) {
788 reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
789 priv->phyaddr = reg;
790 } else {
791 debug("phy-handle does not exist under tsec %s\n", dev->name);
792 return -ENOENT;
793 }
794
795 offset = fdt_parent_offset(gd->fdt_blob, offset);
796 if (offset > 0) {
797 reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
798 priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520);
799 } else {
800 debug("No parent node for PHY?\n");
801 return -ENOENT;
802 }
803
804 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset,
805 "phy-connection-type", NULL);
806 if (phy_mode)
807 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
808 if (pdata->phy_interface == -1) {
809 debug("Invalid PHY interface '%s'\n", phy_mode);
810 return -EINVAL;
811 }
812 priv->interface = pdata->phy_interface;
813
814 /* Initialize flags */
815 priv->flags = TSEC_GIGABIT;
816 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
817 priv->flags |= TSEC_SGMII;
818
819 mdio_info.regs = priv->phyregs_sgmii;
820 mdio_info.name = (char *)dev->name;
821 ret = fsl_pq_mdio_init(NULL, &mdio_info);
822 if (ret)
823 return ret;
824
825 /* Reset the MAC */
826 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
827 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
828 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
829
830 priv->dev = dev;
831 priv->bus = miiphy_get_dev_by_name(dev->name);
832
833 /* Try to initialize PHY here, and return */
834 return !init_phy(priv);
835}
836
837int tsec_remove(struct udevice *dev)
838{
839 struct tsec_private *priv = dev->priv;
840
841 free(priv->phydev);
842 mdio_unregister(priv->bus);
843 mdio_free(priv->bus);
844
845 return 0;
846}
847
848static const struct eth_ops tsec_ops = {
849 .start = tsec_init,
850 .send = tsec_send,
851 .recv = tsec_recv,
852 .free_pkt = tsec_free_pkt,
853 .stop = tsec_halt,
854#ifdef CONFIG_MCAST_TFTP
855 .mcast = tsec_mcast_addr,
856#endif
857};
858
859static const struct udevice_id tsec_ids[] = {
860 { .compatible = "fsl,tsec" },
861 { }
862};
863
864U_BOOT_DRIVER(eth_tsec) = {
865 .name = "tsec",
866 .id = UCLASS_ETH,
867 .of_match = tsec_ids,
868 .probe = tsec_probe,
869 .remove = tsec_remove,
870 .ops = &tsec_ops,
871 .priv_auto_alloc_size = sizeof(struct tsec_private),
872 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
873 .flags = DM_FLAG_ALLOC_PRIV_DMA,
874};
875#endif /* CONFIG_DM_ETH */