| mvgbe.h (606fddd76c7a045c09d544357806b0b4de4845c7) | mvgbe.h (fb7310769882c2fb9716352a78744327e72c2430) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * based on - Driver for MV64360X ethernet ports 8 * Copyright (C) 2002 rabeeh@galileo.co.il --- 16 unchanged lines hidden (view full) --- 25#define PHYADR_MASK 0x0000001f 26#define PHYREG_MASK 0x0000001f 27#define QTKNBKT_DEF_VAL 0x3fffffff 28#define QMTBS_DEF_VAL 0x000003ff 29#define QTKNRT_DEF_VAL 0x0000fcff 30#define RXUQ 0 /* Used Rx queue */ 31#define TXUQ 0 /* Used Rx queue */ 32 | 1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * based on - Driver for MV64360X ethernet ports 8 * Copyright (C) 2002 rabeeh@galileo.co.il --- 16 unchanged lines hidden (view full) --- 25#define PHYADR_MASK 0x0000001f 26#define PHYREG_MASK 0x0000001f 27#define QTKNBKT_DEF_VAL 0x3fffffff 28#define QMTBS_DEF_VAL 0x000003ff 29#define QTKNRT_DEF_VAL 0x0000fcff 30#define RXUQ 0 /* Used Rx queue */ 31#define TXUQ 0 /* Used Rx queue */ 32 |
| 33#ifndef CONFIG_DM_ETH |
|
| 33#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) | 34#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) |
| 35#endif |
|
| 34#define MVGBE_REG_WR(adr, val) writel(val, &adr) 35#define MVGBE_REG_RD(adr) readl(&adr) 36#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) 37#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) 38 39/* Default port configuration value */ 40#define PRT_CFG_VAL ( \ 41 MVGBE_UCAST_MOD_NRML | \ --- 432 unchanged lines hidden (view full) --- 474 u16 l4i_chk; /* CPU provided TCP Checksum */ 475 u16 byte_cnt; /* Descriptor buffer byte count */ 476 u8 *buf_ptr; /* Descriptor buffer ptr */ 477 struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ 478}; 479 480/* port device data struct */ 481struct mvgbe_device { | 36#define MVGBE_REG_WR(adr, val) writel(val, &adr) 37#define MVGBE_REG_RD(adr) readl(&adr) 38#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) 39#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) 40 41/* Default port configuration value */ 42#define PRT_CFG_VAL ( \ 43 MVGBE_UCAST_MOD_NRML | \ --- 432 unchanged lines hidden (view full) --- 476 u16 l4i_chk; /* CPU provided TCP Checksum */ 477 u16 byte_cnt; /* Descriptor buffer byte count */ 478 u8 *buf_ptr; /* Descriptor buffer ptr */ 479 struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ 480}; 481 482/* port device data struct */ 483struct mvgbe_device { |
| 484#ifndef CONFIG_DM_ETH |
|
| 482 struct eth_device dev; | 485 struct eth_device dev; |
| 486#endif |
|
| 483 struct mvgbe_registers *regs; 484 struct mvgbe_txdesc *p_txdesc; 485 struct mvgbe_rxdesc *p_rxdesc; 486 struct mvgbe_rxdesc *p_rxdesc_curr; 487 u8 *p_rxbuf; 488 u8 *p_aligned_txbuf; | 487 struct mvgbe_registers *regs; 488 struct mvgbe_txdesc *p_txdesc; 489 struct mvgbe_rxdesc *p_rxdesc; 490 struct mvgbe_rxdesc *p_rxdesc_curr; 491 u8 *p_rxbuf; 492 u8 *p_aligned_txbuf; |
| 493 494#ifdef CONFIG_DM_ETH 495 phy_interface_t phy_interface; 496 unsigned int link; 497 unsigned int duplex; 498 unsigned int speed; 499 500 int init; 501 int phyaddr; 502 struct phy_device *phydev; 503 struct mii_dev *bus; 504#endif |
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| 489}; 490 491#endif /* __MVGBE_H__ */ | 505}; 506 507#endif /* __MVGBE_H__ */ |